用于连续Σ-Δ调制器的2 bit/cycle SAR量化器

提出了一种用于连续Σ-Δ调制器的新颖的2 bit/cycle SAR量化器。该量化器可缩短SAR量化周期。将该量化器应用于调制器后,调制器的采样速率可提高1.5倍。SAR量化器的单电容阵列可有效减小最后一级积分器的负载。利用基因遗传算法,分析了该量化器引入的较大的环路延时(ELD)的影响,并优化了其补偿支路系数K_c。对0.75倍采样周期进行延时补偿,获得性能更好的噪声整形函数。相比传统调制器,该调制器的信噪比提高了5 dB。     

一种高性能、低功耗音频ΣA调制器

设计了一个应用于18位高端音频模数转换器(ADC)的三阶低功耗Σ△调制器.调制器采用2-1级联结构,通过优化调制器系数来提高其动态范围,并减小调制器输出频谱中的杂波.电路设计中采用栅源自举技术实现输入信号采样开关,有效提高了采样电路的线性度;提出一种高能效的A/AB类跨导放大器,在仅消耗0.8mA电流的情况下,达到100V/μs以上的压摆率.针对各级积分器不同的采样电容,逐级对跨导放大器进行进一步功耗优化.调制器在中芯国际0.18μm混合信号CMOS工艺中流片,芯片核心面积为1.1mm×1.0mm.测试结果表明在22.05kHz带宽内,信噪失真比和动态范围分别达到91dB和94dB.在3.3V电源电压下,调制器功耗为6.8mW,适合于高性能、低功耗音频模数转换器应用.     

一种高精度音频Σ-Δ调制器的研究

简要介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器.该电路采用Chartered 0.5 μm标准CMOS工艺实现,工作电源电压为5 V,在工作频率为6.144 MHz、过采样率为128时,输入带内信噪比可达107 dB.     

一种低压低功耗高精度Σ-Δ调制器

设计了一种应用于智能传感器的3阶3位量化离散时间Σ-Δ调制器。采用低失真的CIFF前馈结构,降低了对运算放大器输出摆幅的要求。基于改进的Class AB结构的电流镜跨导运算放大器(OTA),提出了带电容增益复位的有源加法器,降低了加法器中OTA对压摆率的要求,减小了调制器的功耗。采用TSMC 0.18 μm 1P4M CMOS 工艺进行设计与仿真。结果表明,在1 V电源电压下,能够实现有效位数大于16位的高精度,无杂散动态范围(SFDR)达到105 dB,调制器的整体功耗为340 μW。     

一种低电压工作的高速开关电流Σ-Δ调制器

基于作者先前提出的时钟馈通补偿方式的开关电流存储单元及全差分总体结构,本文设计了一种二阶开关电流Σ-Δ调制器.工作中采用TSMC 0.35μm CMOS数字电路工艺平台,在低电压工作下进行电路参数优化.实验表明,调制器在3.3V工作电压、10MHz采样频率、64倍过采样率下实现10-bit精度.与已有类似研究相比,本工作在相当的精度条件下,实现了低电压、视频速率的工作.     

一种应用于无线通信的低电压低功耗Σ-D调制器的设计

文章首先分析了低电压对于低功耗CMOSΣ-"调制器设计提出的挑战,使用了自顶向下的设计策略,利用Hspice和Simulink对开关电容放大器和开关电路非理想特性建模,通过Matlab优化低功耗结构的运算放大器电路参数,最后给出了系统仿真结果。仿真结果显示,使用0.18#m2p6mCMOS工艺设计的Σ-"调制器在1.5V低电源电压条件下,信号带宽为200KHz,峰值信噪比达到93.5dB,动态范围为96.3dB,满足了GSM/PCS1800/DCS1900等无线应用的要求。     

一种低电压3阶4位前馈Σ-Δ调制器

介绍了一种应用于无线通信领域的低电压、带有前馈结构的3阶4位单环Σ-Δ调制器。为了降低Σ-Δ调制器的功耗,跨导放大器采用了带宽展宽技术。采用TSMC 0.13 μm CMOS工艺对电路进行仿真,仿真结果显示,当工作电压为1.2 V、采样频率为64 MHz、过采样比为16、信号带宽为2 MHz时,电路的SNDR达81 dB,功耗仅为7.78 mW。     

增量型Σ-Δ调制器优化设计算法研究北大核心

提出了一种用于增量型Σ-ΔADC的调制器设计的算法。该算法针对增量型Σ-ΔADC中的积分器系数进行优化，采用两步式搜索的方法，对可能的最优解组合进行多次求解与对比分析。基于该算法，设计了一种16位40 kS/s增量型Σ-ΔADC。可以对ADC电路的有效精度和输入采样速率这两个性能指标进行有效调节及优化。仿真结果表明，采用所提出的优化设计算法可以将ADC的输入采样速度由40 kS/s提升到51 kS/s,或者将ADC的ENOB由13.76 bit提高到14.72 bit,且不增加额外功耗。     

一种高精度音频Σ-Δ调制器的研究北大核心

介绍了Σ-Δ调制器的基本原理,设计了一种适合数字音频应用的16位Σ-Δ调制器。该电路采用Chartered 0.5μm标准CMOS工艺实现,工作电源电压为5V,在工作频率为6.144MHz、过采样率为128时,输入带内信噪比可达107dB。     

一种高精度单环高阶Σ-Δ调制器

设计了一种高精度单环3阶Σ-Δ调制器。阐述了Σ-Δ调制器的结构,确定了前馈因子和增益因子等重要参数。对调制器的各种非理想因素,如时钟抖动、开关非线性、采样电容kT/C噪声等,进行了量化分析和行为级建模。采用MATLAB工具进行了系统验证。验证结果表明,调制器的采样频率为100 kHz,信噪比为99 dB,信噪比最大值为104.2 dB,有效精度达16 位。     

一种采用斩波一稳零技术的低功耗Delta—Sigma调制器的设计

采用TSMC0．18μm CMOS混合信号1P6M工艺实现了一种应用于信号检测系统的低功耗Delta--Sigma调制器．该调制器采用单环积分器级联反馈（CIFB）结构降低了电路的复杂度,并采用Chopper-Stabilization技术降低了系统的直流失调和1／f噪声,提高了电路的低频特性．调制器采用1．8V电源电压,整体功耗仅为2mW,版图尺寸1．25×1．3mm^2．仿真结果表明,该调制器在50kHz信号带宽范围内,可以达到92dB的信噪失真比,99．3dB的动态范围和15bits的有效位数,满足传感器信号检测系统的要求．     

利用PI技术实现Σ-Δ调制器的研究

提出了一种新的低通Σ－Δ调制器,该结构利用流水交叉（ＰＩ）技术对信号进行开采样和降采样,从而达到多路复用的目的。当把各路信号串联时,增加一些有限的电路就可以实现高阶的Σ－Δ调制器。     

一种低功耗16bit音频 Sigma-Delta 调制器的设计

设计了一款工作在1．8 V电源电压下、功耗仅为1．8 mW、精度为16 bit ,优化系数（FOM ）达170的音频sigma-delta调制器．其过采样率为128,采用3阶噪声整形．为了降低功耗,采用前馈结构以及单比特量化．通过采用PM OS管实现局部反馈,有效提升了调制器性能．调制器采用SM IC 0．18μm工艺实现,通过对系统结构和运算放大器、比较器等电路子模块的分析,完成整体电路和版图设计．在SS工艺角下,仿真表明本文设计的调制器性能良好,在20kHz的带宽内可达到100．8dB的信噪比（SNR）,折合有效位16 bits精度要求．     

A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator

A sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using voltage multipliers or bootstrapping switches. A two-path structure is applied to relax the settling requirement. Implemented in a 0.25-m one-poly, five-metal standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 58.2 db and a dynamic range (DR) of 64 db in a 60 KHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm².     

基于开关运放的低功耗逐次逼近ADC设计

基于UMC 0.18 混合信号工艺,设计了一种低功耗逐次逼近ADC,重点考虑了功耗的优化和电路的改进,采用了开关运放技术,降低了传统缓冲器30%左右的能量消耗,同时比较器低功耗的设计也使该ADC节能的优点更加突出,同时比较器采用了失调校准技术,这样就能够满足10 bit精度的要求.在电源电压1.8 V、采样频率100 kHz的条件下,仿真得到该逐次逼近ADC信噪比为61.66 dB,而静态功耗仅为26μW.该设计的芯片版图面积为1 mm×1mm.     

低功耗-高速-高精度SAR ADC的FoM函数研究

SAR ADC适合工作在中级转换速度(Msample/s,Gsample/s),是低功耗和高精度的信号处理应用的最佳选择.为了更好地指导折中设计,基于梳理传统SAR ADC的FoM(Figure of Merits)函数的优缺点,保持寻求最小优值的方式,突出压缩优值变化范围的新优点,利用4参数构造出新的SAR ADC的...     

基于累加器结构的Delta-Sigma调制器的噪声分析

采用Delta-Sigma结构的调制器可降低锁相环路中小数分频时所产生的量化噪声对系统的影响。通过分析Delta-Sigma工作原理推导其噪声传输函数,得出增加Delta—Sigma调制器的阶数或增加过采用率均能减小量化噪声功率。累加器结构的3阶内插型Delta—Sigma调制器结构简单,可有效降低芯片面积,且内插型结构适合以尽量降低环路噪声为目标的设计。     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

A Prototype Bandpass Sigma-Delta Modulator Employing Crystal Resonator

This paper describes an initial work on a second-order bandpass Sigma-delta modulator employing crystal resonator. The aim of this work is to explore the possibilities of realizing bandpass sigma-delta modulator using non-electronic resonators, such as micro-mechanical resonators. The initial study is based on crystal resonators as they have similar characteristics as the other types of resonator and are readily available. In order to obtain the desired loop transfer function, a compensation circuit is proposed to cancel the anti-resonance in the crystal resonator. The modulator chip is fabricated in a 0.6-μ m CMOS process. The bandpass noise shaping is demonstrated in the experiment with a 1- and 8-MHz crystal resonator, respectively. Yong Ping Xu graduated from Nanjing University, P.R. China in 1977. He received his Ph.D. from University of New South Wales (UNSW) Australia, in 1994. From 1978 to 1987, he was with Qingdao Semiconductor Research Institute, P.R.China, initially as an IC design engineer, and later the deputy R&D manager and the Director. From 1993 to 1995, he worked on an industry collaboration project with GEC Marconi, Sydney, Australia, at the same university, involved in design of sigma-delta ADCs. He was a lecturer at University of South Australia, Adelaide, Australia from 1996 to 1998. He has been with the Department of Electrical and Computer Engineering, National University of Singapore since June 1998 and is now an Associate Professor. His general research interests are in the areas of mixed-signal and RF integrated circuits, and integrated MEMS and sensing systems. He is a Senior Member of IEEE. Xiaofeng Wang was born in Shangqiu, China, in 1980. He received B.Eng. degree from Northwestern Polytechnical University, Xi'an, China, in 2000 and M. Eng. degree from National University of Singapore, Singapore, in 2003, both in electrical engineering. He is currently working toward the Ph.D. degree at Tufts University, Medford, USA. His research is on high speed ADC design. Wai Hoong Sun was born in Taiping, Malaysia in 1976. He received the B. App. Sc. (Honours) degree in electrical engineering from the University of Toronto, Canada in 1999. After graduating, he joined Sharp Electronics Singapore as an R&D Engineer where he was involved in FPGA and digital IC design of display related circuits. In 2001 and 2002, he did full time research in the National University of Singapore on bandpass sigma-delta modulators. During that period, he was also a Graduate Tutor in electronics for second year electrical and computer engineering students. He then joined Philips Electronics Singapore in 2002 as a Lead Engineer. He did board-level designs for LCD and plasma televisions. He was also development project leader for a project that was successful in bringing to the market a range of LCD and plasma televisions. Currently, he is a Hardware Architect where he is responsible for the system-level electrical design of the television board.     

一种14位、1.4MS/s、多位量化的级联型Σ△调制器

在 0 .6μm CMOS工艺条件下设计了一种适合 DECT(Digital Enhanced Cordless Telephone)标准的 1 .4MS/s Nyquist转换速率、1 4位分辨率模数转换器的ΣΔ调制器。该调制器采用了多位量化的级联型 (2 -1 -1 4b)结构 ,通过 Cadence Spectre S仿真验证 ,在采样时钟为 2 5 MHz和过采样率为 1 6的条件下 ,该调制器可以达到 86.7d B的动态范围 ,在 3 .3 V电源电压下其总功耗为 76m W。