A comprehensive study of polysilicon resistors for CMOS ULSI applications

The characteristics of polysilicon resistors for CMOS ULSI applications have been investigated. Based on the presented sub-quarter micron CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-silicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyse and calculate some important parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure. Furthermore, the characteristics of voltage-coefficient resistor, temperature-coefficient resistor, and resistor mismatching are also studied. An interesting sine-wave voltage-dependent characteristic due to the strong relation to the R_interface has been modelled in this paper. This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-quarter micron CMOS ULSI technology.     

Microstructure and electrical characterization based on AFM of very high-doped polysilicon grains

In this work, we demonstrate that atomic force microscopy allows topography measurement as well as the local electrical properties of very high-doped polysilicon film prior to any subsequent annealing. AFM and TEM observations showed the columnar microstructure of the polysilicon layer. The electrical effect of this microstructure was characterized using SCM, KFM and C-AFM. Each electric mode gives additional information on the local properties of the polysilicon layer.     

基于CCD与CMOS的图像传感技术

概述了CCD图像传感器的原理、特点及发展趋势。对CMOS图像传感器的结构和工作原理,尤其是CMOS与CCD两类图像传感之间的不同进行综述。重点介绍了CMOS图像传感器的研究现状和发展趋势。     

运用第一性原理研究氧化锌电阻阀片中氧空位与掺杂条件下ZnO晶体电学性质

为了比较Nb_2O_5、MnO_2、MgO三种添加剂对氧化锌电阻阀片电学性能影响,在微观层面模拟Nb、Mn、Mg三种元素分别掺杂ZnO完整超晶胞和带有氧空位缺陷的ZnO超晶胞,并运用第一性原理分析掺杂晶胞的特性.本文计算了晶体结构、掺杂形成能、氧空位形成能、能带结构、态密度、载流子迁移率、电导率等.结果表明,掺入Nb原子的掺杂体系晶格体积最大,Mg掺杂体系的形成能最大,稳定性最弱,Nb掺杂氧空位形成能最低,更容易引入氧空位.Nb掺杂的ZnO超晶胞禁带宽度最小,氧空位缺陷增大掺杂晶体的禁带宽度.在相同掺杂浓度和同等条件下,Mn掺杂的晶体电导率最高.     

CMOS阵列响应过程中的电串扰特性研究

在利用CMOS阵列探测器成像时,探测阵列单元间的串扰将直接影响器件成像质量。为了更好地了解串扰对器件响应过程的影响,针对CMOS图像传感器的电串扰特性进行了分析,建立了电串扰数学分析模型,对电串扰的大小进行了定量计算。具体分析了不同扩散长度、感光面积、耗尽层宽度、像素尺寸和温度对电串扰的影响。分析结果表明,感光面积、耗尽层宽度与像素尺寸对电串扰的影响最大,扩散长度和温度对电串扰的影响相对较小。感光面积由3.8 m2增加到12.8 m2后,归一化的电串扰减小了约13%;像素尺寸由7 m7 m增加为15 m15 m时,电串扰增加了约95.4%;温度由100 K增加到180 K后,电串扰下降了约0.6%。     

The behaviour of mosaic blocks and electrical properties of polysilicon under ion implantation

Abstract

The change in microstrains ε, block sizes L and in the temperature dependences of conductivity of polysilicon with the grain size 30-40nm at N⁺, Ne⁺, P⁺ ion irradiation has been studied. It is shown that ε increases while L practically is not changing up to amorphization. The change in conductivity is governed by an increase in the density of states near the Fermi level and depends both on the damage rate for the given ions and their chemical activity.     

Microstructure and electrical properties of vanadium-doped zinc oxide-based non-ohmic resistors

The microstructure and non-ohmic properties of the ternary system ZVM were investigated in accordance with Mn₃O₄ content. For all samples, the microstructure of the ternary system ZnO-V ₂O₅-Mn₃O₄ consisted of mainly ZnO grain and secondary phase Zn₃(V O₄)₂. The incorporation of Mn₃O₄ to the binary system ZnO-V ₂O₅ was found to restrict the abnormal grain growth of ZnO. The breakdown voltage in the V-I characteristics increased from 17.5 to 463.5 V/mm with the increase in Mn₃O₄ content. The incorporation of Mn₃O₄ up to 0.5 mol% improved non-ohmic properties by increasing non-ohmic coefficient, whereas the further additions decreased it. The highest non-ohmic coefficient (22.2) was obtained from Mn₃O₄ content of 0.5 mol%. It was found that the highest barrier height at grain boundary was 2.66 eV for Mn₃O₄ content of 0.5 mol%.     

Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage ($I_{\rm sub})$, gate-induced-drain-leakage ($I_{\rm GIDL})$, gate edge-direct-tunnelling leakage ($I_{\rm EDT})$ and band-to-band-tunnelling leakage ($I_{\rm BTBT})$ were analysed. For NMOS, $I_{\rm sub}$ can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.     

45 nm CMOS technology with low temperature selective epitaxy of SiGe

This paper describes the advanced embedded silicon germanium (eSiGe) technologies to apply the 45 nm node CMOS fabrication technology. There are three key techniques as follows. The first technique is a low temperature of epitaxial growth at 550 °C to suppress staking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. We demonstrated the drain current of I_on = 725 μA/μm and I_off = 100 nA/μm for PMOSFET using above these techniques.     

纳米多晶硅薄膜电阻压力和加速度多功能传感器（英）

基于纳米多晶硅薄膜电阻的多功能传感器由压力传感器和加速度传感器构成。纳米多晶硅薄膜电阻构成的两个惠斯通电桥结构分别设计在方形硅膜表面和悬臂梁根部。采用MEMS技术和CMOS工艺在〈100〉晶向单晶硅片上实现压力/加速度传感器芯片制作,利用内引线技术将芯片封装在一个印刷电路板（PCB）上。在室温下,工作电压为5.0 V时,实验结果给出压力传感器灵敏度(a=0)为1.0 mV/kPa,加速度传感器灵敏度(p=0)为0.92 mV/g,可实现外加压力和加速度的测量,具有较好的灵敏度特性且交叉干扰较弱。     

Simulation of CMOS logic inverter based on vertically stacked polycrystalline silicon nanosheet gate-all-around MOSFET and its electrical characteristics

The DC and inverter characteristics for the position of a single grain boundary (GB) in a nanosheet gate-all-around (GAA) MOSFET based on poly-crystalline silicon with three channels were analyzed. For the same channel layer, owing to the band banding by the drain voltage, the GB displays decreasing influence on the current as it moves towards the drain. The GB exhibits the highest on-state current of 6.89 × 10⁻⁴ A/μm when it is located at the drain. The DC characteristics determine the noise margin and delay time of the inverter. The higher the induced current, the lower the noise margin and delay time of the NMOS leading to improved characteristics of the inverter. The delay time when the GB existed in the drain, was considered to be the best in terms of DC performance as it was the lowest at 6.47 ps and showed 8.3% improvement in the switching characteristics.     

Material requirements and design considerations for Si/SiGe heterojunction CMOS

Five vertical architecture options for SiGe/Si heterojunction CMOS devices are compared using technology computer-aided design. The benefit of using SiGe over conventional MOSFETs is set to increase for future technology generations. We investigate the impact of material degradation, to determine the minimum requirements needed for HMOS to offer real advantages over conventional CMOS.     

Effects of Proton Irradiation on a CMOS Image Sensor

We perform 9 MeV proton irradiation of a complementary metal oxide semiconductor （CMOS） image sensor at doses from 1 × 10^9 to 4 × 10^10 cm^-2. In general, the average brightness of dark output images increases with an increasing dose, and reaches the maximum at 1 × 10^10 cm^-2. The captured colour images become very blurry at 4 × 10^10 cm^-2. These can be explained by change of concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of CMOS image sensor calculated by the TRIM simulation programme with dose.     

Modeling of Multilayer Suspended Microstrip Line and its Discontinuities on CMOS Grade Silicon Substrate for Millimeter Wave Integrated Circuit Applications

Transmission line parameters such as characteristic impedance Z₀, effective dielectric constant ε_eff, attenuation constant α of suspended microstrip line on multilayer low resistively silicon substrate are investigated using full wave FEM simulator HFSS. Effect of variation in the thickness of Si₃N_4, polyimide and metal layers on attenuation are studied. Due to suspended nature, significant reduction in transmission loss is observed in the simulation at 60 GHz frequency. Discontinuities such as open end, gap and step in width of strip conductor are analyzed to extract their lumped equivalent circuits which can be used in the design of integrated circuits.     

基于CMOS图像传感器的微型无人机遥感系统设计

为了实现微小型无人机航空遥感,设计了一种基于CMOS图像传感器的微小型无人机的可见光遥感系统.系统采用CMOS图像传感器替代CCD,利用时序发生模块(Field-Prog Rammble Array,FPRA)实现了控制时序、数据缓存和硬件彩色插值,C8051F单片机作为主控核心,采用FLASH作为数据存储单元,设计了PAL制视频信号生成电路.介绍了所用CMOS图像传感器的特性,分析了Bayer颜色格式进行彩色插值恢复标准RGB颜色格式的硬件实现与软件算法.整个系统重量约20 g,功耗约2 W.在一款翼展800 mm的无人机上实现了遥感拍照,给出了处理后的拍照结果.     

Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor(CMOS) on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.     

Influence of annealing temperature on structural,electrical and optical properties of WSi2

WSi₂ polycrystalline films of different thicknesses were prepared by low pressure chemical vapor deposition on silicon wafers, and their crystallization properties were studied as a function of the annealing temperature. Structural measurements were performed by X-ray diffraction, detailing for the first time the phase transition from the amorphous to the hexagonal structure at an annealing temperature 380° C and from hexagonal to tetragonal above 700° C. The electrical sheet resistance showed the same transition temperatures.Optical characterization was performed by spectroscopic ellipsometry, and the real and imaginary part of the complex refractive index were obtained as a function of the annealing temperature in the 0.25–0.9 m wavelength range. A broad optical band was found for samples annealed up to 700° C, while for higher annealing temperatures a transparency region for wavelengths greater than 0.5 m and some significant structures appear. A corresponding behavior was observed in the infrared reflectance spectra. Furthermore, it was shown that the determination of the thickness of SiO₂ grown on WSi₂ requires a multilayer model, taking into account the transparency of tetragonal WSi₂.     

Theoretical analysis and experimental application of CDS CMOS integrated circuit for uncooled infrared focal plane arrays

In this paper, a typical correlated double sampling (CDS) complementary metal oxide semiconductor (CMOS) circuit for uncooled infrared focal plane array (IRFPA) is theoretically analyzed, the key factor of CDS CMOS integrated circuit is pointed out, and a new CDS integrated circuit which is high correlative for low-frequency noise is applied in an experimental readout chip for uncooled IRFPA. Theoretical analysis indicates that the sample transfer function of a noise source acted on by CDS processing is related to noise frequency and sampling time interval and the key factor of CDS circuit for reducing or eliminating noise in readout integrated circuit is the sampling time interval. The experimental readout chip with high noise-correlative CDS integrated circuit is fabricated to verify the theoretical analysis, which can be applied to uncooled IRFPAs.     

用于粒子探测器的CMOS FET采样保持电路的设计与仿真(英文)

介绍了一个峰保持电路。该电路适用于silicon strip,Si(Li),CdZn Te and CsI等探测器,实现采样-保持功能。已成功进行了基于CMOSFET的采样-保持电路的设计和仿真,通过使用Proteus的PSPICE仿真器和BSIMV3.3模型参数完成了电路性能的仿真。同时,实现了采样时间可在60ns到4.44s范围内进行选择,该电路具有较好的线性。     

数码相机CMOS图像传感器的特性参数与选择

介绍了数码相机的核心器件———CMOS图像传感器的特性参数和在数码相机设计过程中CMOS图像传感器的选择。选择CMOS图像传感器,不仅需要考虑包括传感器的尺寸、像素总数和有效像素数、最小照度、动态范围、灵敏度、分辨力、光电响应不均匀性以及光谱响应等在内的特性参数,而且还要考虑电源管理和功耗、模数转换位数、开发的简便性以及成本等因素。