p型金属氧化物半导体场效应晶体管界面态的积累对单粒子电荷共享收集的影响

由于负偏置温度不稳定性和热载流子注入,p型金属氧化物半导体场效应晶体管(pMOSFET)将在工作中不断退化,而其SiO₂/Si界面处界面态的积累是导致其退化的主要原因之一. 采用三维器件数值模拟方法,基于130 nm体硅工艺,研究了界面态的积累对相邻pMOSFET之间单粒子电荷共享收集的影响. 研究发现,随着pMOSFET SiO₂/Si界面处界面态的积累,相邻pMOSFET漏端的单粒子电荷共享收集量均减少. 还研究了界面态的积累对相邻反相器中单粒子电荷共享收集 关键词： 负偏置温度不稳定性 电荷共享收集 双极放大效应 单粒子多瞬态     

0.18 μm部分耗尽绝缘体上硅互补金属氧化物半导体电路单粒子瞬态特性研究

利用脉冲激光入射技术研究100级0.18 μm部分耗尽绝缘体上硅互补金属氧化物半导体反相器链的单粒子瞬态效应, 分析了激光入射器件类型及入射位置对单粒子瞬态脉冲传输特性的影响. 实验结果表明, 单粒子瞬态脉冲在反相器链中的传输与激光入射位置有关, 当激光入射第100级到第2级的n型金属-氧化物-半导体器件, 得到的脉冲宽度从287.4 ps增加到427.5 ps; 当激光入射第99级到第1级的p型金属-氧化物-半导体器件, 得到的脉冲宽度从150.5 ps增加到295.9 ps. 激光入射点靠近输出则得到的瞬态波形窄; 靠近输入则得到的瞬态波形较宽, 单粒子瞬态脉冲随着反相器链的传输而展宽. 入射器件的类型对单粒子瞬态脉冲展宽无影响. 通过理论分析得到, 部分耗尽绝缘体上硅器件浮体效应导致的阈值电压迟滞是反相器链单粒子瞬态脉冲展宽的主要原因. 而示波器观察到的与预期结果幅值相反的正输出脉冲, 是输出节点电容充放电的结果.     

锗硅异质结晶体管单粒子效应激光微束模拟

对国产锗硅异质结双极晶体管(SiGe HBT)进行了单粒子效应激光微束辐照试验,观测SiGe HBT单粒子效应的敏感区域,测试不同外加电压和不同激光能量下SiGe HBT集电极瞬变电流和电荷收集情况,并结合器件结构对试验结果进行分析。试验结果表明:国产SiGe HBT位于集电极/衬底结内的区域对单粒子效应敏感,波长为1064 nm的激光在能量约为1.5 nJ时诱发SiGe HBT单粒子效应,引起电流瞬变。入射激光能量增强,电流脉冲增大,电荷收集量增加;外加电压增大,电流脉冲的波峰增大;SiGe HBT的单粒子效应与外加电压大小和入射激光能量都相关,电压主要影响瞬变电流的峰值,而电荷收集量主要依赖于入射激光能量。     

不同偏置影响锗硅异质结双极晶体管单粒子效应的三维数值仿真研究

针对国产锗硅异质结双极晶体管(SiGe HBT),采用半导体器件三维计算机模拟工具,建立单粒子效应三维损伤模型,研究不同偏置状态对SiGe HBT单粒子效应的影响.分析比较不同偏置下重离子入射器件后,各端口电流瞬变峰值和电荷收集量随时间的变化关系,获得SiGe HBT单粒子效应与偏置的响应关系.结果表明:不同端口对单粒子效应响应的最劣偏置不同,同一端口电荷收集量和瞬变电流峰值的最劣偏置也有所差异.载流子输运方式变化和外加电场影响是造成这种现象的主要原因.     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

锗硅异质结双极晶体管单粒子效应加固设计与仿真

本文设计了一种通过在版图布局中引入伪集电极的方法来提高锗硅异质结双极晶体管(SiGe HBT)抗单粒子性能的方法. 利用半导体器件模拟工具, 针对加固前后的SiGe HBT开展了单粒子效应仿真模拟, 分析了伪集电极对SiGe HBT电荷收集机理的影响. 结果表明, 引入的伪集电极形成的新的集电极-衬底结具有较大的反偏能力, 加固后SiGe HBT伪集电极通过扩散机理, 大量收集单粒子效应产生的电荷, 有效地减少了实际集电极的电荷收集量, 发射极、基极电荷收集量也有不同程度的降低, 加固设计后SiGe HBT 的单粒子效应敏感区域缩小, 有效的提高了SiGe HBT 器件抗单粒子效应辐射性能. 此项工作的开展为SiGe HBT电路级单粒子效应抗辐射加固设计打下良好的基础.     

22 nm工艺超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应研究

利用计算机辅助设计技术数值仿真工具, 研究22 nm工艺技术节点下超薄体全耗尽绝缘体上硅晶体管单粒子瞬态效应, 系统地分析了掺杂地平面技术、重离子入射位置、栅功函数和衬底偏置电压对于单粒子瞬态效应的影响. 模拟结果表明, 掺杂地平面和量子效应对于单粒子瞬态效应影响很小, 重离子入射产生大量电荷, 屏蔽了初始电荷分布的差异性. 单粒子瞬态效应以及收集电荷和重离子入射位置强相关, 超薄体全耗尽绝缘体上硅最敏感的区域靠近漏端. 当栅功函数从4.3 eV变化到4.65 eV时, 单粒子瞬态电流峰值从564 μA减小到509 μA, 收集电荷从4.57 fC减小到3.97 fC. 超薄体全耗尽绝缘体上硅器件单粒子瞬态电流峰值被衬底偏置电压强烈调制, 但是收集电荷却与衬底偏置电压弱相关. 关键词： 超薄体全耗尽绝缘体上硅 单粒子瞬态效应 电荷收集 数值仿真     

重离子导致的锗硅异质结双极晶体管单粒子效应电荷收集三维数值模拟

针对国产锗硅异质结双极晶体管(SiGe HBTs), 采用半导体器件模拟工具, 建立SiGe HBT单粒子效应三维损伤模型, 研究影响SiGe HBT单粒子效应电荷收集的关键因素. 分析比较重离子在不同位置入射器件时, 各电极的电流变化和感生电荷收集情况, 确定SiGe HBT电荷收集的敏感区域. 结果表明, 集电极/衬底结内及附近区域为集电极和衬底收集电荷的敏感区域, 浅槽隔离内的区域为基极收集电荷的敏感区域, 发射极收集的电荷可以忽略. 此项工作的开展为下一步采用设计加固的方法提高器件的抗辐射性能打下了良好的基础. 关键词： 锗硅异质结双极晶体管 单粒子效应 电荷收集 三维数值仿真     

SiGe BiCMOS低噪声放大器激光单粒子效应研究

随着CMOS工艺的日益成熟和SiGe外延技术水平的不断提高, SiGe BiCMOS低噪声放大器(LNA)广泛应用于空间射频收发系统的第一级模块. SiGe HBT作为SiGe BiCMOS LNA的核心器件,天然具有优异的低温特性、抗总剂量效应和抗位移损伤效应的能力,然而,其瞬态电荷收集引起的空间单粒子效应是制约其空间应用的瓶颈问题.本文基于SiGe BiCMOS工艺低噪声放大器开展了单粒子效应激光微束实验,并定位了激光单粒子效应敏感区域.实验结果表明, SiGe HBT瞬态电荷收集是引起SiGe BiCMOS LNA单粒子效应的主要原因. TCAD模拟表明,离子在CMOS区域入射时,电离径迹会越过深沟槽隔离结构,进入SiGe HBT区域产生电子空穴对并引起瞬态电荷收集. ADS电路模拟分析表明,单粒子脉冲瞬态电压在越过第1级与第2级之间的电容时,瞬态电压峰值骤降,这表明电容在传递单粒子效应产生的瞬态脉冲过程中起着重要作用.本文实验和模拟工作为SiGe BiCMOS LNA单粒子效应抗辐射设计加固提供了技术支持.     

基于55 nm DICE结构的单粒子翻转效应模拟研究

单粒子翻转(single event upset, SEU)是器件在辐照空间中应用的关键难题,本文以55 nm加固锁存单元为研究载体,通过三维数值模拟方法,获得了重离子不同入射条件下的线性能量转移(linear energy transfer, LET)阈值和电压脉冲变化曲线,研究了双互锁存储单元(dual interlockded storage cell, DICE)的抗辐照性能和其在不同入射条件下的SEU效应.研究表明,低LET值的粒子以小倾斜角入射器件时,降低了器件间的总电荷收集量,使得主器件节点的电压峰值和电压脉宽最小,器件SEU敏感性最低;由于空穴与电子迁移率的差异,导致DICE锁存器中Nhit的入射角敏感性远大于Phit;合理调节晶体管间距可以削弱电荷共享效应,使得从器件总电荷收集量减小,仿真计算得到此工艺下晶体管间距不能小于1.2μm.相关仿真结果可为DICE锁存单元单粒子效应的物理机制研究和加固技术提供理论依据和数据支持,有助于加快存储器件在宇航领域的应用步伐.     

Parasitic bipolar amplification in single event transient and its temperature dependence

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in single event transient (SET) current of single transistor and its temperature dependence are studied. We quantify the contributions of different current components in SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of single transistor.     

Parasitic bipolar amplification in a single event transient and its temperature dependence

Using three-dimensional technology computer-aided design (TCAD) simulation, parasitic bipolar amplification in a single event transient (SET) current of a single transistor and its temperature dependence are studied. We quantify the contributions of different current components in a SET current pulse, and it is found that the proportion of parasitic bipolar amplification in total collected charge is about 30% in both 130-nm and 90-nm technologies. The temperature dependence of parasitic bipolar amplification and the mechanism of the SET pulse are also investigated and quantified. The results show that the proportion of charge induced by parasitic bipolar increases with rising temperature, which illustrates that the parasitic bipolar amplification plays an important role in the charge collection of a single transistor.     

Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.     

Fin width and height dependence of bipolar amplification in bulk FinFETs submitted to heavy ion irradiation

Fin FET technologies are becoming the mainstream process as technology scales down. Based on a 28-nm bulk pFin FET device, we have investigated the fin width and height dependence of bipolar amplification for heavy-ion-irradiated Fin FETs by 3D TCAD numerical simulation. Simulation results show that due to a well bipolar conduction mechanism rather than a channel(fin) conduction path, the transistors with narrower fins exhibit a diminished bipolar amplification effect, while the fin height presents a trivial effect on the bipolar amplification and charge collection. The results also indicate that the single event transient(SET) pulse width can be mitigated about 35% at least by optimizing the ratio of fin width and height, which can provide guidance for radiation-hardened applications in bulk Fin FET technology.     

Experimental and simulation studies of single-event transient in partially depleted SOI MOSFET

In this study, we investigate the single-event transient(SET) characteristics of a partially depleted silicon-on-insulator(PDSOI) metal-oxide-semiconductor(MOS) device induced by a pulsed laser.We measure and analyze the drain transient current at the wafer level. The results indicate that the body-drain junction and its vicinity are more SET sensitive than the other regions in PD-SOI devices.We use ISE 3D simulation tools to analyze the SET response when different regions of the device are hit. Then, we discuss in detail the characteristics of transient currents and the electrostatic potential distribution change in devices after irradiation. Finally, we analyze the parasitic bipolar junction transistor(p-BJT) effect by performing both a laser test and simulations.     

Mechanism of single-event transient pulse quenching between dummy gate isolated logic nodes

As integrated circuits scale down in size,a single high-energy ion strike often affects multiple adjacent logic nodes.The so-called single-event transient(SET)pulse quenching induced by single-event charge sharing collection has been widely studied.In this paper,SET pulse quenching enhancement is found in dummy gate isolated adjacent logic nodes compared with that isolated by the common shallow trench isolation(STI).The physical mechanism is studied in depth and this isolation technique is explored for SET mitigation in combinational standard cells.Three-dimensional(3D)technology computer-aided design simulation(TCAD)results show that this technique can achieve efficient SET mitigation.     

Effect of body biasing on single-event induced charge collection in deep N-well technology

As the device size decreases, the soft error induced by space ions is becoming a great concern for the reliability of integrated circuits(ICs). At present, the body biasing technique is widely used in highly scaled technologies. In the paper, using the three-dimensional technology computer-aided design(TCAD) simulation, we analyze the effect of the body biasing on the single-event charge collection in deep N-well technology. Our simulation results show that the body biasing mainly affects the behavior of the source, and the effect of body biasing on the charge collection for the n MOSFET and p MOSFET is quite different. For the n MOSFET, the RBB will increase the charge collection, while the FBB will reduce the charge collection. For the p MOSFET, the effect of RBB on the SET pulse width is small, while the FBB has an adverse effect. Moreover, the differenceof the effect of body biasing on the charge collection is compared in deep N-well and twin well.     

Three-dimensional simulation of fabrication process-dependent effects on single event effects of SiGe heterojunction bipolar transistor

The fabrication process dependent effects on single event effects(SEEs) are investigated in a commercial silicon–germanium heterojunction bipolar transistor(SiGe HBT) using three-dimensional(3D) TCAD simulations. The influences of device structure and doping concentration on SEEs are discussed via analysis of current transient and charge collection induced by ions strike. The results show that the SEEs representation of current transient is different from representation of the charge collection for the same process parameters. To be specific, the area of C/S junction is the key parameter that affects charge collection of SEE. Both current transient and charge collection are dependent on the doping of collector and substrate. The base doping slightly influences transient currents of base, emitter, and collector terminals. However, the SEEs of SiGe HBT are hardly affected by the doping of epitaxial base and the content of Ge.     

New insight into the parasitic bipolar amplification effect in single event transient production

In this paper, a new method is proposed to study the mechanism of charge collection in single event transient (SET) production in 90 nm bulk complementary metal oxide semiconductor (CMOS) technology. We find that different from the case in the pMOSFET, the parasitic bipolar amplification effect (bipolar effect) in the balanced inverter does not exist in the nMOSFET after the ion striking. The influence of the substrate process on the bipolar effect is also studied in the pMOSFET. We find that the bipolar effect can be effectively mitigated by a buried deep P⁺-well layer and can be removed by a buried SO₂ layer.