小尺寸单轴应变Si PMOS沟道晶面/晶向选择实验新发现

小尺寸单轴应变Si p型金属氧化物半导体(PMOS)沟道反型层迁移率与晶面/晶向密切相关,应变PMOS优化设计时应合理选择沟道的晶面/晶向.目前,文献已有1.5 GPa应力强度下单轴应变Si PMOS沟道反型层迁移率按晶面/晶向排序的理论模型.然而,在器件实际制造过程中,覆盖SiN应力膜工艺是固定的,由于沟道弹性劲度系数具有各向异性,这样,不同晶面/晶向应变PMOS沟道所受应力强度不同,进而导致在实际工艺下沟道反型层迁移率晶面/晶向排序理论模型"失效".针对该问题,本文采用中国科学院微电子研究所40 nm工艺流程制备了不同晶面/晶向40 nm沟道小尺寸单轴应变Si PMOS与未应变Si PMOS,并通过器件转移特性测试,获得了小尺寸单轴应变Si PMOS反型层迁移率晶面/晶向排序结论.此有关小尺寸单轴应变Si PMOS沟道反型层迁移率晶面/晶向排序的相关结论,由于考虑了工艺实现因素,与文献理论预测排序结果相比,更适于指导实际器件制造;相关分析方法也可为其他应变材料沟道MOS相关问题的解决提供重要技术参考.     

漏致势垒降低效应对短沟道应变硅金属氧化物半导体场效应管阈值电压的影响

结合应变硅金属氧化物半导体场效应管(MOSFET)结构,通过求解二维泊松方程,得到了应变Si沟道的电势分布,并据此建立了短沟道应变硅NMOSFET的阈值电压模型.依据计算结果,详细分析了弛豫Si_1－βGe_β中锗组分β、沟道长度、漏电压、衬底掺杂浓度以及沟道掺杂浓度对阈值电压的影响,从而得到漏致势垒降低效应对小尺寸应变硅器件阈值电压的影响,对应变硅器件以及电路的设计具有重要的参考价值. 关键词： 应变硅金属氧化物半导体场效应管 漏致势垒降低 二维泊松方程 阈值电压模型     

TiO2和SiO2薄膜应力的产生机理及实验探索

对最常用的TiO₂和SiO₂薄膜应力, 包括应力模型、应力测试方法和不同实验条件下的应力测试结果作了研究.基于曲率法模型，对TiO₂和SiO₂单层膜和多层膜进行了实验测试，得到了一些有价值的结果，特别是离子辅助淀积和基板温度等工艺参数对薄膜应力的影响.提出了薄膜聚集密度是应力的重要因素，低聚集密度产生张应力，而高聚集密度产生压应力.在多层膜中通过调节工艺参数，适当地控制张应力或压应力，可使累积应力趋向于零. 关键词： 薄膜应力 离子辅助淀积 聚集密度     

ECRCVD技术淀积太阳电池的减反膜

本文报道了用电子回旋共振化学气相淀积(ECRCVD)技术实现了低温(50℃)淀积SiON/SiN膜作硅太阳电池减反射膜的实验研究.探讨了影响薄膜性能的主要工艺参数,设计了具有较佳抗反效果的双层减反膜,并对膜层的反射率和太阳电池参数进行了测定.结果表明:该减反膜具有良好的减反效果,能实现较宽波段范围内的均匀增透,使太阳电池短路电流密度提高了42%,电池转换效率提高了45%.     

纳米尺度下Si/Ge界面应力释放机制的分子动力学研究

采用分子动力学方法研究了纳米尺度下硅(Si)基锗(Ge)结构的Si/Ge界面应力分布特征,以及点缺陷层在应力释放过程中的作用机制.结果表明:在纳米尺度下, Si/Ge界面应力分布曲线与Ge尺寸密切相关,界面应力下降速度与Ge尺寸存在近似的线性递减关系;同时,在Si/Ge界面处增加一个富含空位缺陷的缓冲层,可显著改变Si/Ge界面应力分布,在此基础上对比分析了点缺陷在纯Ge结构内部引起应力变化与缺陷密度的关系,缺陷层的引入和缺陷密度的增加可加速界面应力的释放.参考对Si/Ge界面结构的研究结果,可在Si基纯Ge薄膜生长过程中引入缺陷层,并对其结构进行设计,降低界面应力水平,进而降低界面处产生位错缺陷的概率,提高Si基Ge薄膜质量,这一思想在研究报道的Si基Ge膜低温缓冲层生长方法中初步得到了证实.     

使用SiNx原位淀积方法生长的GaN外延膜中的应力研究

采用低压MOCVD系统，在生长过程中使用SiN_x原位淀积的方法产生纳米掩模，并 在纳米掩模上进行选区生长和侧向外延制备了GaN外延薄膜.使用拉曼光谱和光荧光的手段对 GaN外延膜中的残余应力进行了研究.研究发现，用SiN_x原位淀积出纳米掩模后 ，GaN生长将由二维向三维转变，直到完全合并为止.利用拉曼光谱和光荧光谱分别研究了薄 膜中的残余应力，两者符合得很好；这种方法生长出的GaN薄膜的应力分布较传统的侧向外 延更加均匀；并且从中发现随着生长过程中SiN_x原位淀积时间的增加，生长在 其上的GaN外延膜中的残余应力减小.这是因为，随着SiN_x原位淀积时间的增加 ，SiN_x纳米掩模的覆盖度也增大.因此侧向外延区的比例增大，残余应力随之减 小. 关键词： GaN x原位淀积')" href="#">SiN_x原位淀积 拉曼 光荧光 残余应力     

激光限制结晶技术制备nc-Si/SiO2多层膜

在等离子体增强化学气相淀积系统中，采用aSi:H层淀积和原位等离子体氧化相结合的逐层生长技术制备了aSi:H/SiO_2多层膜.在激光诱导限制结晶原理基础上，使用KrF准分子脉冲激光为辐照源，对aSi:H/SiO_2多层膜进行辐照，使纳米级厚度的aSi:H子层晶化.Raman散射谱和电子衍射谱的结果表明，经过激光辐照后纳米Si颗粒在原始的aSi:H子层内形成，晶粒尺寸可以根据aSi:H层的厚度精确控制.还研究了样品的光致发光（PL）特性以及激光辐照能量密度对PL性质的影响. 关键词： 脉冲激光 多层膜 限制结晶     

激光等离子体淀积硅膜

本工作研究了低温、低压下硅薄膜的激光淀积过程,获得均匀性好,平方厘米量级的多晶和非晶态薄膜。仔细测量了淀积过程的最佳条件,在380℃基片温度做得多晶膜。利用有共振吸收的光学击穿以及气体被击穿后产生爆炸波导致高能Si原子产生的模型,讨论了激光等离子体CVD动力学过程。发现TEACO₂激光击穿SiH₄,以及诱发的爆炸波对硅膜生长有重要作用。理论算得的硅膜生长面积和晶态结构与实验定性符合。 关键词：     

γ射线作用下氧化铪基MOS结构总剂量效应研究

使用原子层淀积方法得到了7.8 nm厚度的HfO₂薄膜并通过直接溅射金属铝电极得到了Al/HfO₂/Si MOS电容结构,测量得到了HfO₂基MOS结构在60Co γ射线辐照前后的电容-电压特性,使用原子力显微镜得到了HfO₂薄膜在辐照前后的表面微观形貌,使用X射线光电子能谱方法测量得到了HfO₂薄膜在辐照前后的化学结构变化。研究发现,使用原子层淀积方法制备的HfO₂薄膜表面质量较高;γ射线辐照在HfO₂栅介质中产生了数量级为1012 cm-2的负的氧化层陷阱电荷;HfO₂薄膜符合化学计量比,介质内部主要的缺陷为氧空位且随着辐照剂量的增加而增加,说明辐照在介质中引入了陷阱从而导致MOS结构性能的退化。     

应变SiGe p 型金属氧化物半导体场效应管栅电容特性研究

由于台阶的出现, 应变SiGe p型金属氧化物半导体场效应管 (pMOSFET) 的栅电容特性与体Si器件的相比呈现出很大的不同, 且受沟道掺杂的影响严重. 本文在研究应变SiGe pMOSFET器件的工作机理及其栅电容C-V 特性中台阶形成机理的基础上, 通过求解器件不同工作状态下的电荷分布, 建立了应变SiGe pMOSFET栅电容模型, 探讨了沟道掺杂浓度对台阶的影响. 与实验数据的对比结果表明, 所建立模型能准确反映应变SiGe pMOSFET器件的栅电容特性, 验证了模型的正确性. 该理论为Si基应变金属氧化物半导体(MOS)器件的设计制造提供了重要的指导作用, 并已成功应用于Si基应变器件模型参数提取软件中, 为Si基应变MOS的仿真奠定了理论基础. 关键词： 应变SiGe pMOSFET 栅电容特性 台阶效应 沟道掺杂     

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g_m) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f_T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.     

Finite-element study of strain field in strained-Si MOSFET

The strain field in the channel of a p-type metal-oxide-semiconductor field effect transistor fabricated by integrating Ge pre-amorphization implantation for source/drain regions is evaluated using a finite-element method combining with large angle convergent-beam electron diffraction (LACBED). The finite-element calculation shows that there is a very large compressive strain in the top layer of the channel region caused by a low dose of Ge ion implantation in the source and drain extension regions. Moreover, a transition region is formed in the bottom of the channel region and the top of the Si substrate. These calculation results are in good agreement with the LACBED experiments.     

异质多晶SiGe栅应变Si NMOSFET物理模型研究

结合了“栅极工程”和“应变工程”二者的优点, 异质多晶SiGe栅应变Si MOSFET, 通过沿沟道方向使用不同功函数的多晶SiGe材料, 在应变的基础上进一步提高了MOSFET的性能. 本文结合其结构模型, 以应变Si NMOSFET为例, 建立了强反型时的准二维表面势模型, 并进一步获得了其阈值电压模型以及沟道电流的物理模型. 应用MATLAB对该器件模型进行了分析, 讨论了异质多晶SiGe栅功函数及栅长度、衬底SiGe中Ge组分等参数对器件阈值电压、沟道电流的影响, 获得了最优化的异质栅结构. 模型所得结果与仿真结果及相关文献给出的结论一致, 证明了该模型的正确性. 该研究为异质多晶SiGe栅应变Si MOSFET的设计制造提供了有价值的参考. 关键词： 异质多晶SiGe栅 应变Si NMOSFET 表面势 沟道电流     

螺旋波等离子体增强化学气相沉积氮化硅薄膜

利用螺旋波等离子体增强化学气相沉积(HWP-CVD)技术，以SiH4和N2为反应气体进行了氮化硅(SiN)薄膜沉积，并研究了实验参量对薄膜特性的影响.利用傅里叶变换红外光谱、紫外—可见光谱和椭偏光检测等技术对薄膜的结构、厚度和折射率等参量进行了测量.结果表明，采用HWP-CVD技术能在低衬底温度条件下以较高的沉积速率制备低H含量的SiN薄膜，所沉积的薄膜主要表现为Si—N键合结构.采用较低的反应气体压强将提高薄膜沉积速率，并使薄膜的致密性增加.适当提高N2/SiH4比例有利于薄膜中H含量的降低. 关键词： 螺旋波等离子体 化学气相沉积 氮化硅薄膜     

单Halo全耗尽应变Si 绝缘硅金属氧化物半导体场效应管的阈值电压解析模型

为了改善金属氧化物半导体场效应管(MOSFET) 的短沟道效应(SCE)、 漏致势垒降低(DIBL) 效应, 提高电流的驱动能力, 提出了单Halo 全耗尽应变硅绝缘体 (SOI) MOSFET 结构, 该结构结合了应变Si, 峰值掺杂Halo结构, SOI 三者的优点. 通过求解二维泊松方程, 建立了全耗尽器件表面势和阈值电压的解析模型. 模型中分析了弛豫层中的Ge组分对表面势、表面场强和阈值电压的影响, 不同漏电压对表面势的影响, Halo 掺杂对阈值电压和DIBL的影响.结果表明, 该新结构能够抑制SCE和DIBL效应, 提高载流子的输运效率. 关键词： 应变Si 阈值电压 短沟道效应 漏致势垒降低     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Two-dimensional phosphorus diffusion for soft drains in silicon MOS transistors

Phosphorus has a considerably less steep concentration profile than arsenic. Therefore phosphorus is considered as an alternative dopand for soft drain concepts in future MOS devices. In-diffusion of phosphorus starting from a high surface concentration generatesexcess point defects which diffuse into the depth of the crystal and lead to a tail in the phosphorus concentration profile by considerably enhancing the phosphorus diffusion in this region. It is also well known that the interface between silicon and a non growing oxide acts as a sink for excess point defects. Since source/drain areas of MOS transistors are surrounded by gate and isolation oxides, the question arises how the resulting excess point defect distribution may influence the lateral and vertical diffusion profile of phosphorus and hence the channel length and the junction depth of the source/drain region in a MOS device. We extended the one-dimensional Fair-Tsai model of phosphorus diffusion into two dimensions and incorporated that the interface between silicon and a gate oxide acts as a sink for excess point defects and modifies their distribution. The appropriate code was implemented in the two-dimensional process simulation program LADIS. Based on this extended model two-dimensional simulations of phosphorus drains have been performed and compared to experimental results and to results from other numerical models. It turns out that the presence of the gate oxide reduces the tail in the phosphorus concentration profile, considerably in lateral direction and less pronounced in vertical direction. Limitations of the model will be discussed in detail.     

Channel length effect in a MOSFET structure by scanning capacitance microscopy

Depth dependent carrier density and trapped charges in a metal-oxide-semiconductor field effect transistor (MOSFET) like structure have been studied using scanning capacitance microscopy (SCM). For a MOSFET structure, since minority carrier can be provided by the source and drain diffusions, its response time is shorter than that of metal-oxide-semiconductor (MOS) system. So the high frequency C-V relation is slightly different from that of MOS capacitor and shows the characteristics dependent on the channel length. Bias dependent SCM images which represent the depth dependent carrier density and detrapping time constant of trapped charges in the oxide layer were observed to see the channel effect in a MOSFET structure.     

In-situ SiN combined with etch-stop barrier structure for high-frequency AlGaN/GaN HEMT

The etch-stop structure including the in-situ SiN and AlGaN/GaN barrier is proposed for high frequency applications.The etch-stop process is realized by placing an in-situ SiN layer on the top of the thin AlGaN barrier.F-based etching can be self-terminated after removing SiN,leaving the AlGaN barrier in the gate region.With this in-situ SiN and thin barrier etch-stop structure,the short channel effect can be suppressed,meanwhile achieving highly precisely controlled and low damage etching process.The device shows a maximum drain current of 1022 mA/mm,a peak transconductance of 459 mS/mm,and a maximum oscillation frequency(fmax)of 248 GHz.