A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.This research was sponsored by the Semiconductor Research Corporation, Contract 90-DP-142.     

边界扫描测试结构完备性诊断策略

边界扫描结构完备性测试是在其他任何测试之前建议首先进行的测试操作，以确保边界扫描结构能正常工作。本文在分析了边界扫描结构故障类型与测试原理之后提出了一种完备性诊断策略，并给出了具体实现过程。     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

Partial scan design and test sequence generation based on reduced scan shift method

This paper presents a partial scan algorithm, calledPARES (PartialscanAlgorithm based onREduced Scan shift), for designing partial scan circuits. PARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines proch FFs must be controlled and observed for each test vector. According to the results of similar analysis, PARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then PARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of PARES.     

Partial scan and symbolic test at the register-transfer level

This paper presents a partial scan methodology suited for (pipelined) data paths described at the Register-Transfer level. The method is based on feedback elimination by making existing registers scannable or by adding extra transparent scan registers An optimal set (in terms of area cost) of scan registers is selected using an exact branch and bound algorithm. This approach can deal with complex realistic data paths requiring orders of magnitude lower CPU times than gate devel techniques. Furthermore, our symbolic test pattern generation technique can very effectively deal with the delay in the remaining acyclic sequential circuit parts. This symbolic test method makes various scan schemes possible which ensure a correct assembly and application of the test vectors. They are discussed and compared in terms of hardware requirements, test application times and test accuracy.     

一种基于边界扫描的FIFO测试方法

针对含先进先出存储器(FIFO)电路板故障检测的问题,提出一种基于边界扫描技术编写Macro对FIFO进行读写数据的测试方法,介绍边界扫描技术测试FIFO的基本原理。通过设计适配板,应用边界扫描测试工具ScanWorks,建立边界扫描链路,编写Macro测试代码,利用JTAG接口进行间接控制,实现对FIFO进行故障检测。给出了测试系统硬件框图、简述了适配板设计要点,提供FIFO电路连接图和软件流程图,并分析FIFO测试的完备性,最后还对FIFO进行了测试验证。     

基于SimHydraulic的加注系统建模与故障仿真

航天器在轨服务技术是未来重要的发展方向之一。实际故障数据的获取成本高且风险大,为了研究在轨加注过程中系统的可靠性,得出系统故障征兆并对典型故障进行辨识,采用Matlab 中的 SimHydraulic 对加注系统进行建模。结合在轨加注系统各部分工作原理以及器件物理参数分析及更改的方法,对模型进行参数设置以及器件搭建,最终实现常见故障状态下加注系统参数变化趋势。通过对模型故障仿真分析,为故障诊断专家系统的建立提供推理依据。     

边界扫描测试技术

边界扫描技术是一种标准化的可测试性设计方法,它提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案,极大地方便了系统电路的测试.介绍了边界扫描技术的原理、结构,讨论了边界扫描技术的应用.     

基于边界扫描的EPM9320LC84电路板故障诊断

结合自适应算法、CX-TB导通测试算法以及二进制计数测试序列，给出了用软件控制EPM9320LC84边界扫描链路，以输出图形并采集引脚对图形的响应，然后通过比较输出测试图形与采集测试图形的差异实现芯片I／O引脚印刷电路板故障的诊断方法。该测试图形便于实现，测试方法快捷、通用性强，诊断结果准确，故障覆盖率高。文中在以PC机作为边界扫描测试向量生成和故障诊断的基础上，对单芯片——EPM9320LC84的印刷电路板故障诊断进行了一些讨论。     

IEEE standard 1149.1-1990 on boundary scan: History,literature survey,and current status

From humble beginnings, boundary scan has emerged as a major topic in the area of design-for-test applied to electronic devices, boards, and systems. This article reviews the literature in the field, and outlines the historical development of the new IEEE standard 1149.1–1990.Formerly with Philips CFT Automation, Eindhoven, NL.     

边界扫描器件BSDL描述在测试中的应用

在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试图形生成ATPG与故障诊断软件中。本文以EPM7128SL84芯片为例，说明了其BSDL描述在边界扫描测试程序中的应用方法与要点。     

Output gating performance overhead elimination for scan test

Switching activity is much higher in test mode as compared to normal mode of operation which causes higher power dissipation, and this leads to several reliability issues. Output gating is proposed as a very effective low-power test technique, which is used to eliminate redundant switching activity in the combinational logic of circuit under test (CUT) during the shifting of test vectors in a scan chain. This method reduces the average power significantly, but it introduces performance overhead in normal mode of operation. In this work, a new output gating technique is proposed which eliminates redundant switching activity in combinational logic of CUT during shifting of test vectors without any negative impact on performance as compared to earlier proposed output gating techniques. The proposed design also improves the performance of the scan flop in functional mode with negligible area overhead incurred due to extra transistors. Experimental results show that our design has a more robust performance over wide range of capacitive load as compared to earlier designs.     

基于边界扫描技术的板级BIT设计及测试策略

随着超大规模集成电路(VLSI)、表面安装器件(SMD)、多层印制电路板(MPCB)等技术的发展，常规BIT设计面临挑战。为解决上述问题，本文提出了一种基于边界扫描技术的板级BIT的扫描器件置入法及其测试策略。该方法操作简单，经济实用，一旦广泛使用，无疑将会有很好的军事经济效益。     

IEEE 1149.4标准实验测试结构设计和扩展研究

本文采用复杂可编程逻辑器件（CPLD）和分立器件,设计实现了IEEE 1149.4混合信号边界扫描标准实验测试结构。为了提高互连测试的故障诊断能力,文中对模拟边界模块（ABM）开关结构进行了一些修改。针对ABM单元的这些修改允许测试者可以将模拟输入信号与多个电压进行比较。当测试者在简单互连或扩展互连中遇到桥接故障,扩展的ABM开关结构使得故障更容易探测。     

Economic modeling of board test strategies

A long and deep recession, coupled with continuous competitive pressure to reduce costs, is forcing many companies to review their test strategies. Testing costs have become a more significant proportion of the overall manufacturing cost even though manufacturing yields have increased dramatically over the past ten or twelve years. This causes attention to be focused on testing costs as a key source of cost reduction. The increased use of DFT and the integration of design and test are very positive moves towards controlling testing costs but other methods employed can often backfire. The increased use of low priced testers is one such method. The pressure to reduce costs, higher process yields and exhortations that testing adds no value can lead the test engineering manager to take the cheap route. In reality this can often turn out to be an expensive decision. The only way to avoid expensive mistakes is to perform an economic analysis of the alternative courses of action. In most cases this is done, but not always in the right manner or with the necessary amount of detail to make the comparisons meaningful. This article discusses the need for effective cost analysis of test strategies and highlights some of the pitfalls.     

边界扫描SRAM簇板级互连测试研究

由于边界扫描结构的复杂与费用的关系,在现代电子电路中广泛使用的静态随机存取存储器还很少包含边界扫描结构.本文提出了一种能完全实现SRAM簇互连测试的方法,该方法能检测SRAM簇控制线、数据线和地址线的板级互连故障,且测试长度较短.     

I DDQ testing as a component of a test suite: The need for several fault coverage metrics

This article is concerned with the role of I _DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with I _DDQ , scan, timing and functional tests. To realistically fault grade I _DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total I _DDQ failures (parts which fail I _DDQ regardless of whether they fail other tests as well) or unique I _DDQ failures (parts which fail only I _DDQ ). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.     

边界扫描测试技术在雷达BIT电路中的应用

提出了一种采用超大规模集成电路的边界扫描测试技术来设计内建自测试(BIT)电路的方法。此方法利用一片单片机的I/O口线以及超大规模集成电路所具有的边界扫描测试结构来实现对VLST集成电路芯片的故障诊断。     

JTAG测试中扫描链的配置问题研究

分析了常见扫描链路配置中面临的问题,提出了一种扫描链配置方案。结合工程测试中出现的实际问题,给出了有关扫描链路配置的一些建议和注意事项。