用于高速CMOS图像传感器的锁相环模块

随着CMOS图像传感器(CIS)向片上系统化、高度集成化方向发展,片内锁相环(PLL)成为系统不可或缺的片上时钟模块,而高速高集成的CIS对PLL的高频时钟输出能力提出了新的挑战。介绍了一种基于0.13μm CIS工艺设计的电荷泵PLL模块,该模块工作于1.5V电压,利于控制功耗;具备压控振荡器(VCO)电流自偏置和自校准技术,可提供最高频率为480MHz的输出信号和更好的噪声性能;多种输入输出倍频可选功能使其能够满足多样化的片上时钟生成需求,提高可复用性。仿真结果表明,当实现12倍频且输出频率为480MHz时,该PLL模块输出信号的均方根周期抖动为837fs,功耗为2.817mW,满足高速CIS对时钟速度的需求,同时保证了输出时钟的低噪声和模块本身的低功耗。     

高速CMOS图像传感器的信号处理电路设计研究

随着科技的不断发展,我国高速摄影技术水平得到了明显提高,CMOS图像传感器在传统传感器的基础技能上不断革新,因为具备诸多优点,受到了广大用户的欢迎。CMOS图像传感器与普通的传感器相比,只有在切换启动和停止时才会消耗电能,因此符合我国节能环保的概念,而且CMOS图像传感器在实际的使用过程中,由于散热少、污染少,被广泛的应用于我国各类工业的图像传输过程中。因此为了提升我国工业水平,使我国工业发展更加迅速,努力的提升高速CMOS图像传感器的技术研发水平,因此设计更加合理的信号处理电路非常必要。     

基于CMOS图像传感器的高速小型化成像系统设计

基于LUPA1300-2型CMOS图像传感器设计了一套高速、高分辨率、小型化,低功耗的成像系统。以FPGA作为系统的时序控制程序开发平台,采用Verilog硬件描述语言设计了传感器驱动、数据处理、通信和数据传输等模块程序,并对各模块的功能与结构进行了分析和说明。基于本文提出的成像系统框架开发了硬件电路,然后对整个系统进行了成像实验。结果表明,该成像系统驱动时序合理,与计算机通信正常,数据传输准确,图像质量高,系统运行稳定。     

用于CMOS图像传感器的列并行高精度ADC

设计了一种适用于CMOS图像传感器的列并行Single-slopeADC。采用的列并行ADC,同时对多数据源并行处理,增强了数据吞吐量,特别适用于CMOS图像传感器大像素阵列的数据处理。分析了影响ADC精度的因素,并给出了减小失调的方法。该ADC在0.35μm工艺下成功流片验证,测试结果表明,该ADC,在50MS/s的高数据吞吐量下,实现了CMOS图像传感器的8bit精度的设计要求和17.35mW的低功耗,以及0.62mm2的芯片面积。ADC的DNL=0.8LSB,INL=1.096LSB。     

一种用于CMOS图像传感器的锁相环设计

设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环(CPPLL)电路.基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成.系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求.在输入参考频率为5 MHz时,压控振荡器(VOC)输出频率范围为40～217 MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5 mW,环路带宽为567 kHz,相位裕度为57°,相位噪声为一105 dBc/Hz@1 MHz.     

一种用于CMOS图像传感器的Column-Level模数转换器

设计了一种用于CMOS图像传感器(CIS)的column-level模数转换器(ADC)。它由一种新型斜坡发生器构成,具有分辨率可调的特点,而且以简单的结构实现了高精度和低功耗,占用较小的版图面积。基于0.35μm2P4M标准CMOS工艺,8bit ADC转换时间约50μs,最大线性误差小于±0.5LSB。在分辨率为640×480pixel的CIS中,每列共用1个比较器,提高了传感器的吞吐速率,帧频约40fps;3.3V电压下ADC总功耗不超过27mW,占用版图面积约0.5mm2。     

列级反馈降低复位噪声的CMOS图像传感器

提出了一种通过放大器和开关建立起反馈环路,基于列级反馈复位的低噪声CMOS图像传感器（CIS）。设计的CMOS图像传感器采用0.18μm CIS工艺进行了流片,测试结果表明,通过对噪声带宽与反馈放大器的带宽匹配,在复位脉冲下降沿时间为6µs的条件下,传感器的复位噪声减少25dB,满足低照度高速的安防监视系统的应用需求。     

应用于CMOS图像传感器的高速列级ADC设计

针对CMOS图像传感器的高速化设计提出了一种列级ADC电路,其采用单斜式ADC与TDC结合的方式,通过时钟信号约束比较器输出,在量化的最后一个时钟周期内产生与电压对应的时间差值.利用TDC将该差值转换为相应的数字码并与单斜式ADC的量化结果做差,实现高精度转换的同时显著提高了 ADC的量化速度.基于0.18 μm CM...     

用于CMOS图像传感器芯片的版权保护盲水印算法

提出了一种易于硬件实现的、用于图像版权保护的自适应盲水印算法。利用R、G和B分量在图像信息中各自的不同特点做不同处理;根据人眼的视觉特性,通过对图像G分量纹理强度分析自适应地选择合适的水印拉伸因子,从R分量中提取图像内容来加密水印,对B分量进行DCT变换来嵌入不可见盲水印。采用伪随机序列发生器实现水印置乱,基于DCT中低频系数求均值来嵌入盲水印,大大降低了硬件消耗。实验结果表明,算法对噪声干扰、滤波、锐化、剪裁和模糊处理具有很好的鲁棒性,提取出的水印的归一化相关系数均在0.5之上,大于人眼可识别的检测阈值。     

用于CMOS图像传感器的列并行RSD循环ADC

设计了一种用于CMOS图像传感器的列并行RSD循环ADC.转换和采样同步进行,速度比传统的循环ADC提高了1倍,适用于高速实时系统的应用.将采样保持,精确乘2和像素信号的FPN噪声消除功能用1个运放和6个电容来实现,大大缩小了面积.采用RSD算法,不但降低了对比较器的精度要求,并且实现了较高的线性度.通过失调反向存储,基本消除运放失调引入的列FPN噪声.该ADC在0.18μm工艺下,实现了10位精度和500 KS/S的高转换速度.ADC的DNL= 0.5/-0.5 LsB,INL= 0.1/-1.5 LSB.     

CMOS图像传感器中电荷非完全转移的影响分析

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size.Based on the emission current theory,a qualitative photoresponse model is established to the preliminary prediction.Further analysis of noise for incomplete charge transfer predicts the noise variation.The test pixels were fabricated in a specialized 0.18μm CMOS image sensor process and two different processes of buried N layer implantation are compared.The trend prediction corresponds with the test results,especially as it can distinguish an unobvious incomplete charge transfer.The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.     

Measurement of charge transfer potential barrier in pinned photodiode CMOSimage sensors

The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was performed in detail on the principle of the proposed method. Application of the measurements on a prototype PPD-CIS chip with an array of 160 × 160 pixels is demonstrated. Such a method intends to shine new light on the guidance for the lag-free and high-speed sensors optimization based on PPD devices.     

基于多次N型离子注入对4T像素光吸收效率及电荷转移的优化

为了提高像素的光吸收效率,优化电荷的转移,提出了多次N型离子注入的方法形成PPD的N埋层。通过不同能量的N型离子注入拓展了N埋层的吸收深度从而提高了光的吸收效率;通过在N埋层形成横向的非均匀掺杂分布,减小了电荷转移的势垒,优化了电荷的转移。仿真结果表明,经过改进后长波长光的吸收效率可以提高约10％,电荷转移后残留的电子浓度大约可以减小两个数量级。     

Collection efficiency and charge transfer optimization for a 4-T pixel with multi n-type implants

In order to increase collection efficiency and eliminate image lag,multi n-type implants were introduced into the process of a pinned-photodiode.For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed,which expanded the vertical collection region. To reduce the image lag,a horizontal gradient doping concentration eliminating the potential barrier waalso formed by multi n-type implants.The simulation result shows that the collection efficiency can be improved by about 10%in the long wavelength range and the density of the residual charge is reduced from 2.59×10⁹ to 2.62×10⁷ cm^-3.     

Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO₂ interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO₂ interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO₂ interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.     

Highly durable organic photodetector for complementary metal oxide semiconductor image sensors

Utilizing organic electronics compatible with conventional semiconductor fabrication processes is extremely difficult because of their low chemical resistivity and poor environmental durability. To preserve the intrinsic functionality of organic materials, only a few fabrication processes can be used. Moreover, it is essential to achieve process expandability and silicon-process compatibility to develop high-resolution electronics suitable for mass production. Therefore, we developed wet-process-compatible organic photodetectors by replacing the conventional shadow-mask process with photolithography. This suppresses particle deposition during the serial fabrication processes, providing high operational stability. The fabricated green organic photodiodes exhibit a low dark current (1.0 × 10⁻¹¹ A/cm²) with high photon–electron conversion efficiency (EQE = 65%). The charge collection and charge separation efficiencies are stable (η_cc = 84.6% and η_cs = 97.7%, respectively). Moreover, the organic semiconductors are compatible with conventional wet- and dry-etching processes owing to thin-film encapsulation layers. Finally, the novel organic image sensor can withstand 500 h under 85 °C/85% relative humidity and 1000 thermal cycles (−55–125 °C). Because of its robustness and strong barrier properties, the novel process architecture reported herein can be extended to any organic electronic devices, including widely commercialized organic light-emitting diodes and organic photovoltaic devices.