CMOS器件中电荷泵过程的图解表示

我们提出了一种以图解的方式来理解复杂的电荷泵浦 ( CP ) 测量过程的方法。这里我们定义了电荷泵浦测量中的快速和慢速两种缺陷陷阱,并用图解的方式清晰直观地解释了电荷泵浦测量中出现的脉冲上升下降时间相关现象、频率相关现象、快速和慢速成分与测量电压相关现象以及几何效应对电荷泵浦测量的影响。由于电子和空穴的捕获截面不对称,并且测量到的电荷泵浦电流 ( Icp ) 是由捕获截面较小的电子或者空穴成分决定,所以慢速陷阱的电荷泵测量中含有动态和稳态两个过程。我们还用这个图解的方法讨论了最新发展的改良电荷泵浦 ( MPC ) 方法的合理性。     

Boundary condition and initial value effects in the reaction-diffusion model of interface trap generation/recovery

time, tn, is observed in the diffusion limited region of the RD model.     

电荷泵技术在高压 MOS晶体管可靠性研究中的应用

主要阐述了电荷泵技术在14 V HV MOS晶体管可靠性研究中的应用.使用了一种改进的电荷泵技术分析了经过热载流子加压后的器件特性.使用这种方法,我们可以精确描述器件损伤的位置和程度,以及可以精确评估由于HCI效应引起的界面缺陷的变化,为器件优化与工艺改进提供重要参考信息.     

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET.A 0.12μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method.The trapped charge distribution with a narrow peak can be precisely characterized with this method,which shows good consistency with the measured threshold voltage.     

一种应用于纳米尺度器件陷阱电荷表征的新型改进电荷泵方法

随着器件特征尺寸的缩小,热载流子带来的器件蜕化效应越来越严重。电荷泵方法可用于表征陷阱电荷的分布。但由于局部阈值电压窄峰的影响,传统电荷泵法在测试陷阱电荷分布时存在误差。本文提出了一种改进型电荷泵测试方法,可用于精确提取纳米尺度器件中陷阱电荷的横向分布。 本文采用0.12微米的SONOS器件来验证这一方法的有效性。通过编程控制,使SONOS器件形成大约50纳米的阈值电压窄峰。采用新方法测试得到的陷阱电荷分布与测试得到的阈值电压有较好的一致性。     

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

高k栅介质的可靠性问题

随着集成电路特征尺寸的不断缩短,利用先进的高k/金属栅堆叠来取代传统的SiO2/多晶硅栅结构成为微电子技术发展的必然,确保这些新的栅极堆叠类型具有足够的可靠性是非常重要的.综述了高k栅介质可靠性的研究现状,阐明了瞬态充电效应导致的阈值电压不可靠问题,对偏压温度不稳定现象(BTI)和高k击穿特性进行了探讨.     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.     

搭桥晶粒多晶硅薄膜晶体管直流电应力下的退化行为与退化机制研究

研究了搭桥晶粒(BG)多晶硅薄膜晶体管(TFT)在直流电应力下的退化行为和退化机制。与普通多晶硅TFT相比,BG多晶硅TFT展现出更好的直流应力可靠性。主要体现在BG多晶硅TFT拥有更好的直流负偏压温度不稳定性(NBTI)可靠性,更好的直流自加热(SH)可靠性,更好的直流热载流子(HC)可靠性。有源沟道区的BG结构是上述直流应力可靠性提高的主要原因。更好的NBTI的可靠性主要源于沟道内的硼氢键的形成;更好的SH可靠性主要源于在沟道长度方向上更快的焦耳热扩散率;更好的HC可靠性主要源于漏端横向电场(Ex)的减弱。所有的测试结果都表明,这种高性能高可靠性的BG多晶硅TFT在片上系统中具有很大的应用前景。     

CMOS图像传感器中电荷非完全转移的影响分析

A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size.Based on the emission current theory,a qualitative photoresponse model is established to the preliminary prediction.Further analysis of noise for incomplete charge transfer predicts the noise variation.The test pixels were fabricated in a specialized 0.18μm CMOS image sensor process and two different processes of buried N layer implantation are compared.The trend prediction corresponds with the test results,especially as it can distinguish an unobvious incomplete charge transfer.The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.     

Analysis of trap effect on reliability using the charge pumping technology in La-incorporated high-k dielectrics

In this paper, reliability characteristics of nMOSFETs with La-incorporated HfSiON and HfON and metal gate have been studied. HfLaSiON shows greater device degradation by hot carrier (HC) stress than by positive bias temperature (PBT) stress, while HfLaON exhibits similar degradation during HC stress and PBT stress. To evaluate the contribution of bulk trap during PBT stress, a novel charge pumping (CP) technique is applied to extract the distribution of bulk trap (N_bt) before and after PBT stress. To evaluate permanent damage during HC stress, an appropriate selection of frequency range in CP method is considered. The initial interface trap density of HfLaSiON and HfLaON is similar, while the near-interface trap (N_IT) density of HfLaSiON after HC stress is equal or greater than that of HfLaON.     

PMOSFET的NBTI效应

随着工艺的发展,器件尺寸的不断缩小,PMOSFET受负温度不稳定性(NBTI)效应影响而失效的现象愈来愈严重,NBTI效应的影响成为器件可靠性的一个焦点问题.本文综述了NBTI效应的产生机理、影响因素、减缓方法及其相关的一些前沿问题.     

NBTI效应的退化表征

对超深亚微米PMOSFET器件NBTI效应的失效机理和退化表征进行了讨论.反应-扩散模型是最为广泛接受的NBTI退化机理模型,它有效地解释了阈值电压漂移随时间逐渐饱和以及应力去除后NBTI效应部分恢复的退火现象.用阈值电压漂移量表征了NBTI效应的退化,深入讨论了影响NBTI效应的主要因素:应力作用时间、栅氧电场和温度应力,总结了阈值电压漂移与这些因素的关系,给出了一个经验-逻辑推理公式,对公式中的参数提取后可以得到NBTI寿命值,从而实现NBTI效应的可靠性评价.     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

Characterization of ultra-thin SiO2 by capacitance-voltage and charge pumping measurements

In this paper, we present results on electrical measurements of ultra thin SiO₂ layers (from 3.5 nm down to 1.7 nm), used as gate dielectric in metal-oxide-semiconductors (MOS) devices. Capacitance-voltage (C-V) measurements and simulations on MOS capacitors have been used for extracting the electrical oxide thickness. The SiO₂/Si interface and oxide quality have been analyzed by charge pumping (CP) measurements. The mean interface traps density is measured by 2-level CP, and the energy distribution within the semiconductor bandgap of these traps are investigated by 3-level charge pumping measurements. A comparison of the energy distribution of the SiO₂/Si interface traps is made using classical and quantum simulations to extract the surface potential as a function of the gate signal. When the gate oxide thickness <3.5 nm, we prove that it is mandatory to take into account the quantum effects to obtain a more accurate energy distribution of the SiO₂/Si interface traps. We also explain the increase of the apparent interface traps density measured by 2-levels CP with the increase of the oxide thickness, for transistors made from the same technological process.     

基于LiF/Al/F4-TCNQ/NPB电荷产生层的叠层有机电致发光器件的特性研究

采用结构为LiF/Al/F4-TCNQ/NPB的电荷产生层,制备出了双发光单元叠层有机电致发光器件(OLED:Organic Light Emitting Device)。通过对比实验发现当F4-TCNQ层的厚度为8nm、Al层的厚度为5nm时,电荷产生层产生电荷的能力较强且具有良好的透光率。基于此,本文制备了发光层为CBP:6%Ir(ppy)3的叠层OLED,通过与单发光单元OLED的性能比较发现:采用LiF/Al/F4-TCNQ/NPB作为电荷产生层制备的叠层OLED的最大电流效率与功率效率分别为51.6cd/A、28.4lm/W,为单发光单元OLED的2.16倍、1.8倍,此外采用这种结构的电荷产生层有效解决了叠层OLED由于工作电压高而导致功率效率并未得到提升的问题;另一方面,采用有机材料F4-TCNQ代替传统无机金属氧化物作为电荷产生层中的电荷产生部分,能够避免无机金属氧化物高温升华对Al层薄膜的破坏,提升了器件的效率并且降低了器件的roll-off现象。     

注氮剂量对SOI材料埋氧中电荷密度的影响

为对SIMOX SOI材料进行抗总剂量辐照加固,可向材料的埋氧（BOX）层中注入一定剂量的氮元素。但是,研究发现,注氮埋层中的初始电荷密度皆为正值且密度较高,而且随着注氮剂量的增加而上升。注氮埋层中较高的正电荷密度可归因于氮在退火过程中在Si-BOX界面的积累。另外,与注氮埋层不同的是,注氟的埋层却显示出具有负的电荷密度。为得到埋层的电荷密度,测试用样品制成金属-埋氧-半导体(MBS)电容结构,用于进行高频C-V测量分析。     

Influence of nitrogen dose on the charge density of nitrogen-implanted buried oxide in SOI wafers

To harden silicon-on-insulator (SOI) wafers fabricated using separation by implanted oxygen (SIMOX) to total-dose irradiation, the technique of nitrogen implantation into the buried oxide (BOX) layer of SIMOX wafers can be used. However, in this work, it has been found that all the nitrogen-implanted BOX layers reveal greater initial positive charge densities, which increased with increasing nitrogen implantation dose. Also, the results indicate that excessively large nitrogen implantation dose reduced the radiation tolerance of BOX for its high initial positive charge density.The bigger initial positive charge densities can be ascribed to the accumulation of implanted nitrogen near the Si-BOX interface after annealing. On the other hand, in our work, it has also been observed that, unlike nitrogen-implanted BOX, all the fluorine-implanted BOX layers show a negative charge density. To obtain the initial charge densities of the BOX layers, the tested samples were fabricated with a metal-BOX-silicon (MBS) structure based on SIMOX wafers for high-frequency capacitance-voltage (C-V) analysis.     

Transient Performance Estimation of Charge Plasma Based Negative Capacitance Junctionless Tunnel FET

We investigate the transient behavior of an n-type double gate negative capacitance junctionless tunnel field effect transistor (NC-JLTFET). The structure is realized by using the work-function engineering of metal electrodes over a heavily doped n⁺ silicon channel and a ferroelectric gate stack to get negative capacitance behavior. The positive feedback in the electric dipoles of ferroelectric materials results in applied gate bias boosting. Various device transient parameters viz. transconductance, output resistance, output conductance, intrinsic gain, intrinsic gate delay, transconductance generation factor and unity gain frequency are analyzed using ac analysis of the device. To study the impact of the work-function variation of control and source gate on device performance, sensitivity analysis of the device has been carried out by varying these parameters. Simulation study reveals that it preserves inherent advantages of charge-plasma junctionless structure and exhibits improved transient behavior as well.