一种低功耗高频CMOS峰值检测电路

给出了一个低功耗、高频CMOS峰值检测电路,可以用于检测射频信号和基带信号的峰值.该电路的设计基于中芯国际0.35μm标准CMOS工艺.理论分析和后仿真结果都表明,在工艺偏差以及温度变化条件下,当输入信号幅度在400mV以上时检测的误差小于2%,检测带宽可达10GHz以上,整个检测电路的静态电流消耗低于20μA.     

A Low-Power High-Frequency CMOS Peak Detector

给出了一个低功耗、高频CMOS峰值检测电路,可以用于检测射频信号和基带信号的峰值.该电路的设计基于中芯国际0.35μm标准CMOS工艺.理论分析和后仿真结果都表明,在工艺偏差以及温度变化条件下,当输入信号幅度在400mV以上时检测的误差小于2%,检测带宽可达10GHz以上,整个检测电路的静态电流消耗低于20μA.     

Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes

In this investigation we examine different pixel structures and readout principles to be used in imagers fabricated in standard CMOS processes, for example, the 0.5 and 0.35 processes available at the Fraunhofer IMS. The targeted applications are high-speed near-infra-red (NIR) 3-D imaging based on time-of-flight (TOF) measurements. We discuss various issues ranging from charge-coupling possibilities to noise, spectral responsivity and fill-factor, and present an extensive study of pixel configurations based on inverse biased p-n junction and MOS-C based photodetectors. We also discuss the possibilities of using a novel CMOS imaging pixel for TOF imaging applications: the charge-injection photogate (CI-PG) which presents parametric time-compression amplification. Finally, we compare and discuss all the pixel configurations examined.     

一种基于CMOS工艺的电平转换芯片

基于CSMC 2P2M 0.6 μm CMOS工艺设计了一种电平转换芯片.整体电路采用Hspice和CSMC 2P2M的0.6 μm CMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC 2P2M 0.6 μm CMOS 工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与...     

A CMOS Ripple Detector for Voltage Regulator Testing

This paper presents an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The sensor can detect a peak-to-peak ripple voltage of up to 50 millivolts on the 1.2 V supply rail and has 220 MHz bandwidth. The sensor is designed using IBM 90 nm CMOS technology and its functionality is verified in Cadence Virtuoso simulation environment.     

A 300-GHz CMOS 7-by-7 Detector Array for Optics-less THz Imaging with Scan-less Target Object

Journal of Infrared, Millimeter, and Terahertz Waves - In this work, a 300-GHz 7?×?7 detector array based on a 65-nm Si CMOS technology has been developed and transmission imaging...     

Design of a Standard Floating-Point Chip

Some aspects of design of a VLSI floating-point chip, which provides the WE/spl registered/32100 microprocessor with math acceleration capabilities, are described. The chip is implemented in 1.75-/spl mu/m twin-tub CMOS II technology [2] and contains 140 000 transistors.     

CMOS图像采集芯片中噪声抑制新方法研究

本文针对CMOS图像采集芯片中信号的基本特点,对于白噪声的消除,在Donoho提出的基于小波的软阈值和硬阈值去噪法的基础上,将输入信号的信噪比作为去噪参数,研究并提出了适合于CMOS图像采集芯片噪声消除的新方法,并且给出用Matlab仿真的结果。结果表明,当测试信号为Bocks,输入信号信噪比为3dB-13dB时,使用此方法输出信号信噪比比软阈值法平均提高2．2dB,比硬阈值法平均提高0．21dB。     

锂离子电池的保护芯片设计

设计了一种基于CMOS工艺的锂离子电池保护芯片,采用工作在亚阈值区的电路结构,使电路具有高效低耗的特点,能够防止电池在工作过程中出现过充电、过放电、过电流和短路等异常状态。模拟结果表明,该芯片实现了基本保护功能并在功耗方面达到了设计目标。     

CMOS PLL Design in a Digital Chip Environment

CMOS PLLs are becoming increasingly useful for clocksynthesis and recovery in CPU and other digital chip designs.However, the packaging and process are defined to meet the requirementsof the digital chip, not the analog portions of the PLL. Theenvironment defined by the digital requirements includes thepackage, the process and the dominant noise source. Packagesfor complex digital chips are larger and have more complex frequencyand signal integrity characteristics than smaller packages thatare appropriate for dedicated analog chips. Digital CMOS processeslack the quality capacitors, resistors and possible variety ofdevices that may be found in a process developed specificallyfor analog purposes. Digital switching causes significant noisethat dominates the spectrum that the circuit designer must worryabout. This paper considers a typical CMOS PLL design from thedigital chip design viewpoint.     

用单片机制作的遥控回应式报警装置

介绍了一种用单片机和编、解码器结合制作的遥控回应式报警装置的原理和方法，给出了硬件电路和软件流程图。     

A Blind Modulation Type Detector for DPRS Standard

In this paper, some methods allowing automatic discrimination between the types of modulations proposed by the DPRS communication standard are presented. In a non-cooperative context, the receiver must first be able to detect the presence of a modulated signal before eventually carrying out its demodulation (i.e. having access to the information). For this purpose a receiver capable of identifying digital modulations of type M-QAM, 8-PSK and GMSK, proposed by the ETSI–DPRS standard, has been studied. Three detection algorithms have been investigated. The first is based on the observation of the amplitude histograms, the second on the continuous wavelet transform and the third on the maximum likelihood for the joint probability densities of phases and amplitudes. Their performance has been evaluated against signal to noise ratio. Iyad W. Dayoub was born in Messiaf, Syria, in 1969. He received the Dipl.-Ing. degrees in electronic engineering from the University of Tichreen-Syria, in 1993. He received the Dipl.-MS from the University of Nancy-France, in 1997. In 2001, he received the Dipl of Dr.-Ing. degrees in electronics from the University of Valenciennes-France. From 1993 to 1998, he was Engineer in Siemens-Damascus, Syria. From 2000 to 2002, he has been an Instructor and Researcher at the University of Valenciennes, France. Actually, he is assistant Professor at the University of Valenciennes. His current research interests include blind equalization, detection algorithms and radio over fibre networks. Anicet Okassa M’Foubat was born in Okondja, Gabon, in 1979. He received the Dipl.-BS. degrees in electronic engineering from the University of Mons, Belgium, in 2002. He received the Dipl.-MS from the University of Valenciennes-France, in 2004. Since 2004 he is a PHD student at the University of Valenciennes. His current research interests are in blind detection algorithms and multi-users detection for radio-optical networks. Romaric Mvone Evina was born in Minvoul, Gabon, in 1975. He received the Dipl.-BS. Degrees in Physics from the University of Amiens, France, in 2002. He received the Dipl.-MS from the University of Valenciennes-France, in 2003. Since 2003 he is a PhD student at the University of Valenciennes. His current research interests are in blind detection algorithms and equalizers for cellular standards. Jean-Michel Rouvaen was born in 1947. He received his M.S. degree in 1968 and his Ph.D. degree in 1971, from the University of Lille (France). He is now Professor in electronics at University of Valenciennes. Some ten years ago, he was involved in non-linear phenomena, ultrasonics and acousto-optics. His primary research interests are now in signal processing and telecommunication.     

A Novel CMOS Multi-band THz Detector with Embedded Ring Antenna

To overcome the large chip area occupation for the traditional terahertz multi-frequency detector by using the antenna elements in a different frequency, a novel structure for a multi-frequency detector is proposed and studied. Based on the ring antenna detector, an embedded multi-ring antenna with multi-port is proposed for the multi-frequency detector. A single-ring and dual-ring detectors are analyzed and designed in 0.18 μ m CMOS. For the single-ring detector, the best responsivity and NEP is 701 V/W and 261 pW/Hz^0.5 at the frequency of 290 GHz. For the dual-ring detector, the best responsivity is 367 V/W and 297 V/W, NEP is 578 pW/Hz^0.5 and 713pW/Hz^0.5, at the frequency of 600 GHz and 806 GHz, respectively. This embedded multi-ring detector has a simple structure which can be expanded easily in a compact size.     

A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications

This paper presents a novel CMOS impulse radio (IR) ultra-wide-band (UWB) transceiver system design for future contact-less chip testing applications using inductive magnetic coupling as wireless interconnect. The proposed architecture is composed of a simple and robust design of a Gaussian monocycle impulse generator at the transmitter, a wideband short-range on-chip transformer for data transmission, and a g_m-boosted common-gate low-noise amplifier in the UWB receiver path. SpectreRF post-layout simulation with a 90-nm CMOS technology shows that the transceiver operates up to a 5 Gb/s data rate, and consumes a total of 9 mW under a 1-V power supply.     

Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays

High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-mum, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35 mumtimes15 mum and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2-kHz bandwidth is ap110 fA. The maximum charge storage capacity at 2 kHz is 1.26times10⁶ electrons     

A Single CMOS Speech Synthesis Chip and New Synthesis Techniques

A single CMOS speech synthesis LSI, organized as a special purpose microcomputer containing program ROM, RAM, 32K of speech data ROM, and a D/A converter is described in this paper. The chip utilizes new speech synthesis techniques to generate high quality speech, reproducing the natural inflection and intonation of the speaker, and has been used to produce speech at a bit rate of about 3 kbits/s.     

用于数字电视调谐芯片的高线性CMOS VGA

设计了一种适于DVB-C标准的中频可变增益放大器。该放大器由三部分构成:电流调节型可变增益单元、基于差分对管传输特性的指数控制电压产生电路以及一高线性输出级。采用Chartered0.25μm RFCMOS工艺库下流片。测试结果表明,4～49dB的连续增益范围,100MHz的3dB带宽,50Ω负载下的OIP3为16.8dBm。     

基于CMOS工艺的高性能射频滤波器:体声波滤波器(BAW)

过去几年中,随着射频集成电路技术和系统结构的发展,移动电话中射频部分的很多分立器件已被替换。最为明显的就是接收机中分立的低噪声放大器(LNA)和中频(IF)滤波器已经被集成到射频集成电路中。可以预期各射频模块将逐步被集成到标准BiCMOS或CMOS集成电路中,但还是有几类射频元件的集成不太容易做到,其中就包括射频滤波器。所有的移动电话都需要射频滤波器以保护敏感的接收(Rx)信道,使之免受其他用户的发送(Tx)信号及各种射频源产生的噪声干扰。移动电话可能要求当Rx信号比干扰信号强度低120dB时仍能工作。而前置放大器无法提供足够小的互调以满足这种要求。     

一种用于900MHz射频识别(RFID)读写器芯片的1.8VCMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M混合信号CMOS工艺上实现验证.设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能.实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm.该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

一种用于900MHz射频识别（RFID）读写器芯片的1.8V CMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M 混合信号CMOS工艺上实现验证. 设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能. 实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm. 该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.