Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

MOS capacitors obtained by wet oxidation of n-type 4H-SiC pre-implanted with nitrogen

The manufacture process and the electrical characterization of MOS devices fabricated by wet oxidation of N⁺ implanted n-type 4H-SiC are here presented. Different implantation fluence and energy values were used with the aims to study the effect of the N concentration both at the SiO₂/SiC interface and within the SiO₂ film. High doses, able to amorphise a surface SiC layer to take advantage of the faster oxidation rate of amorphous with respect to crystalline SiC, were also evaluated. The electrical quality of the SiO₂/SiC system was characterized by capacitance-voltage measurements of MOS capacitors. The analyses of the collected data show that only the implanted N which is located at the oxide-SiC interfaces is effective to reduce the interface states density. On the contrary, the interface states density remains high (the same of an un-implanted reference sample) when the implanted N is completely embedded in the region consumed by the oxidation. Furthermore, none generation of fixed positive charges in the oxide was found as a consequence of the different N concentrations enclosed in the oxide films. These results were independent of the amorphisation of the implanted layer by the N⁺ ions. Our results demonstrate that by using a suitable N ion implantation and an appropriate wet oxidation treatment, it is possible to obtain a reduced thermal budget process able to decrease the interface state density near the conduction band edge. The proposed approach should be interesting for the development of the MOSFET technology on SiC.     

Investigation of 4H-SiC MOS capacitors annealed in diluted N2O at different temperatures

Thermally grown oxide on 4H-SiC has been post-annealed in diluted N₂O (10% N₂O in N₂) at different temperatures from 900 to 1100 °C. The quality of the nitrided oxide and the SiO₂/4H-SiC interface was investigated by AC conductance and high frequency C-V measurements based on Al/SiO₂/4H-SiC metal-insulator-semiconductor (MOS) structure. It is found that N₂O annealing at 1000 °C produces the lowest interface state density, though the difference is not so significant when compared to the other samples annealed at 900 and 1100 °C. These results can be explained by the high temperature dynamic decomposition process of N₂O. By fitting the AC conductance data, it is found that higher temperature nitridation increases the capture cross-section of the interface traps.     

The Effects of Implant Activation Anneal on the Effective Inversion Layer Mobility of 4H-SiC MOSFETs

In this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC metal oxide semiconductor field-effect transistors (MOSFETs). Initially, lateral n-channel MOSFETs were fabricated with three process splits to investigate phosphorus implant activation anneal temperatures of 1200, 1650, and 1800°C. Mobility results were similar for all three temperatures (using a graphite cap at 1650°C and 1800°C). A subsequent experiment was performed to determine the effect of p-type epi-regrowth on the highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 ? p-type regrowth, while growing 0.5 μm or more appears to be sufficient to grow out of the damaged area. A continuing series of tests are being conducted at present.     

Impurity Deionization Effects on Surface Recombination DC Current-Voltage Characteristics in MOS Transistors

Impurity deionization on the direct-current current-voltage characteristics from electron-hole recombi-nation(R-DCIV)at SiO<,2>/Si interface traps in MOS transistors is analyzed using the steady-state Shockley-Rea-Hall recombination kinetics and the Fermi distributions for electrons and holes.Insignificant distortion is observed over 90%of the bell-shaped R-DCIV curves centered at their peaks when impurity deionization is excluded in the theory.This is due to negligible impurity deionization because of the much lower electron and hole concentrations at the interface than the impurity concentration in the 90% range.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Effect of ionizing radiation on MOS capacitors

A numerical model of metal-oxide-semiconductor (MOS) capacitor has been developed to investigate the effect of ionizing radiation on the characteristics of the device during exposure and also in the post-irradiated condition. The model takes into account the effect of radiation-induced changes in silicon-dioxide as well as in silicon substrate of MOS structure. It is found that the total high frequency capacitance of the device during exposure to radiation is different from its value in the post-irradiated condition. The results of the study are expected to be useful in predicting the behavior of MOS based devices operating in radiation environment.     

The effects of NO passivation on the radiation response of SiO2/4H-SiC MOS capacitors

The radiation response of SiO₂ gate oxides grown on 4H-SiC to NO passivation is presented for the first time. The effects of gamma radiation on Q_eff are similar for n-4H-SiC MOS capacitors both with and without NO passivation, but are different in sign (negative) compared to SiO₂ on Si. The variation in D_it with total dose, however, is different for the passivated versus the unpassivated samples. Comparisons between Si SOI and 4H-SiC suggest that properly passivated SiC MOSFETs should have good radiation tolerance.     

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current-voltage (I-V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I-V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco^®-TCAD). The proposed model also illustrates the effectiveness of the gate-source distance scaling effect compared to the gate-drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I-V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

一种新型的6H-SiC MOS器件栅介质制备工艺

采用干 O2 +CHCCl3(TCE)氧化并进干 /湿 NO退火工艺生长 6H-Si C MOS器件栅介质 ,研究了 Si O2 /Si C界面特性。结果表明 ,NO退火进一步降低了 Si O2 /Si C的界面态密度和边界陷阱密度 ,减小了高场应力下平带电压漂移 ,增强了器件可靠性 ,尤其是湿 NO退火的效果更为明显。     

n型4H-SiCMOS电容的特性

在n型4H-SiC外延层上，采用H2, O2合成的办法，热生长30nm的SiO2层，并制备出Al栅MOS电容，完成了C-V特性的测试和分析工作，根据测试结果得出了SiO2与4H-SiC外延层的界面特性，并计算出n型4H-SiC外延层的掺杂浓度. 结果表明H2, O2合成热生长的SiO2与4H-SiC外延层之间具有较好的界面特性，界面态密度较小. n型4H-SiC外延层的掺杂均匀，浓度为1.84e17cm-3.     

O2+CHCCl3氧化对6H-SiC MOS电容界面特性的改善

采用新颖的干O2 CHCCl3(TCE)氧化工艺，制备了P型和N型6H—SiCMOS电容器，并与常规热氧化工艺以及氧化加NO退火工艺进行了对比实验。结果表明，O2 TCE氧化不仅提高了氧化速率，而且降低了界面态密度和氧化层有效电荷密度，提高了器件可靠性。可以预测，O2 TCE氧化与湿NO退火相结合的工艺是一种有前途的制备高沟道迁移率、高可靠性SiCMOS—FET的栅介质工艺。     

Effects of wet N2O oxidation on interface properties of6H-SiC MOS capacitors

Oxynitrides were grown on n- and p-type 6H-SiC by wet N₂O oxidation (bubbling N₂O gas through deionized water at 95°C) or dry N₂O oxidation followed by wet N₂O oxidation. Their oxide/SiC interfaces were investigated for fresh and stressed devices. It was found that both processes improve p-SiC/oxide but deteriorate n-SiC/oxide interface properties when compared to dry N₂O oxidation alone. The involved mechanism could be enhanced removal of unwanted carbon compounds near the interface due to the wet ambient, and hence a reduction of donor-like interface states for the p-type devices. As for the n-type devices, incorporation of hydrogen-related species near the interface under the wet ambient increases acceptor-like interface states. In summary, wet N ₂O oxidation can be used for providing comparable reliability for nand p-SiC MOS devices, and especially for obtaining high-quality oxide-SiC interfaces in p-type MOS devices     

TCE浓度对热氧化制备6H-SiC MOS特性的影响

研究了新型SiCMOS电容的制备工艺。采用干O2+CHCCl3(TCE)热氧化方法生长6H-SiCMOS氧化层。研究了TCE浓度与SiC/SiO2界面态电荷密度和氧化层电荷密度和应力下平带电压漂移的关系,随着TCE浓度的增加,SiC/SiO2界面态电荷密度和氧化层电荷密度先减小后增大,应力下平带电压漂移减小,得出了最佳TCE:O2浓度比。     

SiO_2/SiC界面的Wet-ROA改性机理研究

高温热氧化法在4H-SiC(0001)晶面上生成SiO2氧化膜,采用湿氧二次氧化(wet-ROA)工艺对样品进行处理,通过测量SiCMOS结构界面电学特性,发现wet-ROA工艺有助于降低界面态密度,改善SiO2/SiC界面电学特性。采用变角X射线光电子能谱(ADXPS)技术对SiO2/SiC界面过渡区进行分析,通过过渡区厚度计算和过渡区成分含量比较,发现湿氧二次氧化工艺可减小过渡区氧化膜厚度,降低过渡区成分含量,进而揭示了降低SiO2/SiC界面态密度,改善界面电学特性的微观机理。     

Effects of high field generation of charge trapping in the oxideand interface traps on MOS capacitors and MOSFETs

Oxide charge trapping and interface state generation phenomena under the various high-field stress conditions have been investigated using capacitors fabricated on both p-and n-type substrates, and p- and n-channel MOSFETs. It was found that prediction based on MOSFET devices yielded shorter lifetimes than predictions based on capacitors     

N型6H-SiCMOS电容的电学特性

在可商业获得的 N型 6 H- Si C晶片上 ,通过化学气相淀积 ,进行同质外延生长 ,在此结构材料上 ,制备 MOS电容 .详细测量并分析了 6 H- Si C MOS电容的电学特性 ,其有效电荷密度为 4.3× 10 1 0 cm- 2 ;Si C与 Si O2 之间的势垒高度估算为 2 .6 7e V;Si C热生长 Si O2 的本征击穿场强 (用累计失效率 5 0 %时的场强来计算 )为 12 .4MV/ cm ,已达到了制作器件的要求 .     

采用Ni/Ti/Ni多层金属在N型4H-SiC衬底改善粘附性和界面的欧姆接触

The Ni/Ti/Ni multilayer ohmic contact properties on a 4H-SiC substrate and improved adhesion with the Ti/Au overlayer have been investigated. The best specific contact resistivity of 3.16 × 10^-5 Ω.cm^2 was obtained at 1050 ℃. Compared with Ni/SiC ohmic contact, the adhesion between Ni/Ti/Ni/SiC and the Ti/Au overlayer was greatly improved and the physical mechanism under this behavior was analyzed by using Raman spectroscopy and X-ray energy dispersive spectroscopy （EDS） measurement. It is shown that a Ti-carbide and Ni-silicide compound exist at the surface and there is no graphitic carbon at the surface of the Ni/Ti/Ni structure by Raman spectroscopy, while a large amount of graphitic carbon appears at the surface of the Ni/SiC structure, which results in its bad adhesion. Moreover, the interface of the Ni/Ti/Ni/SiC is improved compared to the interface of Ni/SiC.