可配置的高码率Turbo码编译码器的设计及实现

Turbo码是一种高效纠错编码技术,其性能可以接近香农极限。由于Turbo码在低信噪比情况下性能优越,同时还拥有较强的抗衰落、抗干扰能力,已被广泛用于信道编码领域。采用可配置的编译码结构,在现场可编程逻辑门阵列（Field Programmable Gate Array,FPGA）实现高码率Turbo码编译码器时,实现较强的数据处理能力和较少的硬件资源占用,并可根据使用场景的不同进行译码参数配置,在Turbo码纠错时间及纠错精度之间寻求平衡。经过ModelSim仿真以及在Artix-7平台上实验,验证了Turbo译码可配置编译码实现的可行性和有效性。     

Turbo码高速译码器设计

Turbo码具有优良的纠错性能,被认为是最接近香农限的纠错码之一,并被多个通信行业标准所采用。Turbo码译码算法相比于编码算法要复杂得多,同时其采用迭代译码方式,以上2个原因使得Turbo码译码器硬件实现复杂,而且译码速度非常有限。从Turbo码高速译码器硬件实现出发,介绍Turbo码迭代译码的硬件快速实现算法以及流水线译码方式,并介绍利用Altera的Flex10k10E芯片实现该高速译码器硬件架构。测试和仿真结果表明,该高速译码器具有较高的译码速度和良好的译码性能。     

CCSDS标准的Turbo译码器的硬件设计

Turbo码具有接近Shannon信道理论极限的译码性能,CCSDS在保留原编码方案的前提下已将其加入遥测信道编码建议书。在简要介绍CCSDS标准的编码结构以后,概述了相应的Turbo码译码器的硬件设计方案。详细介绍了具体的设计流程,最后给出了设计结果。     

基于FPGA的Turbo码译码器的设计

主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,对分量译码器做了详细论述,给出了各子模块原理和ModelSim仿真图形;最后给出了系统仿真的误码率图形。     

利用FPGA实现3GPP Turbo编码译码器

Turbo卷积码(TCC)是3G无线系统中所采用的前向错误校正(FEC)机制的整体部分。然而,Turbo译码器所带来的计算负担非常重,并不太适合采用传统DSP或RISC处理器实现。由于现场可编程逻辑阵列(FPGA)内在的并行结构,FPGA为解决3G基站收发器中所需要的符号速率FEC和其它计算密集的任务提供了一个高性能信号处理平台基础。     

一种基于FPGA的Turbo码译码器的设计

主要论述了一种基于FPGA的Turbo码译码器的设计。首先简单介绍了编码器和交织器的原理;然后介绍了基于Max-Log-MAP算法的译码器原理,详细论述了各个子模块;最后给出了系统仿真的误码率图形。     

跳频系统下Turbo编译码器的设计

在介绍Turbo码编译码原理基础上,针对特定跳频系统,设计了一种Turbo编译码方案。详细论述了该方案中编译码器的设计、建模和仿真过程。该方案中采用MAX-LOG-MAP的迭代译码算法,仿真验证了译码器采用6次迭代可以在保证抗干扰性能的前提下,面向硬件实现计算量适中。因此,该方法具有一定的工程应用价值。     

基于FPGA的Turbo码译码器的设计

介绍了一种基于现场可编程门阵列（FPGA）的Turbo码译码器的完整的设计方案和设计结果,采用Max-Log-MAP译码算法,用Verilog语言编程,提出了正序运算和逆序运算同时进行,以及采用数组型存储器存储中间运算结果的方案,使译码速度得到提高。文中给出了Turbo码译码原理、Max-Log-MAP算法分析、基于FPGA的设计方案及实现框图、算法时序图及速度分析、仿真波形图及性能分析,结果表明,该方案正确可行,译码/纠错正确无误,且译码速度快。     

一种新颖的Turbo码MAP译码器

根据Turbo码trellis结束的情况及Turbo码的特征本文提出了一种新的Turbo码MAP译码器。这是基于MAP译码器中两个组成译码器性能的不一致所作改进,从分析和仿真结果我们可以看到该方法的优势。     

Turbo码的编译码器及性能分析

介绍Turbo码的编译码器和迭代译码器的结构 ,并分析Turbo的性能     

一种低开销双二元turbo译码器设计

设计一种低开销双二元turbo译码器,提出了一种能够适应滑动窗算法的交织器结构,通过与传统方案中的交织器联合使用,大大降低了交织与解交织过程所需要的存储单元.同时将取模归一化(modulo normalization)技术运用到双二元turbo译码器加比选(ACS)模块的设计上,缩短了关键路径的延时,提高了时钟频率和吞吐量.采用FPGA对译码器进行了验证,提出的译码器和传统的译码器相比,存储资源节省12%,和使用存储器存储交织/解交织地址的译码器相比,存储资源节省97%.     

低功耗异步LDPC解码器运算通路设计

本文设计了异步LDPC解码器运算通路,利用异步电路减少信号到达时间不一致引起的毛刺和时钟引起的功耗.利用输入数据的统计特性设计了运算通路中的主要运算单元,减少了冗余运算.本文还实现了同步运算通路和基于门控时钟的运算通路作为比较.三种设计采用相近的架构,在0.18μm CMOS工艺下实现相同的功能.仿真结果表明,提出的异步设计功耗最小,相比于同步设计和基于门控时钟设计,分别节省了42.0%和32.6%的功耗.虽然性能稍逊于同步设计,但优于门控时钟设计.其中,同步设计的延时是1.09ns,基于门控时钟的设计延时是1.61ns,而异步设计则是1.20ns.     

Memory Power Reduction for High-Speed Implementation of Turbo Codes

Turbo codes achieve one of the highest coding gains known and should be the best candidates for error correction in high-speed communication systems. However, the standard implementation of their decoding algorithm suffers from a large latency and high power consumption making them improper for mobile interactive systems. To overcome this drawback, we carefully analyzed the Maximum A Posteriori algorithm, the key-building block of the decoder, and stated that memory accesses are the bottleneck. Therefore, we have systematically optimized the data transfer and storage. This paper presents the main results of this optimization, especially those concerning the memory organization and architecture.Both for the input and the metrics values, a memory sub-layer is introduced such that temporal data locality can be maximally exploited. The architecture is defined to optimally allocate memory units and assign arrays, such that the number of accesses is drastically reduced. The combined optimizations reduce the latency by a factor 600 and the energy per bit by a factor 20, breaking definitely an important obstruction to the application of turbo codes in high-speed communication systems.     

家庭网关SoC DSP 子系统低功耗设计

DSP子系统是家庭网关SoC的关键部分,随着系统工作频率越来越高,系统功耗也越来越大,低功耗设计就极为重要,本文介绍了DSP的时钟配置,尤其是不同工作状态的具体配置,采用关闭DSP ROM,以及状态切换,在正常运行态、待机态、休眠态之间切换DSP子系统工作模式的方法,在系统设计阶段,降低系统功耗的方法和具体系统工作模式转换步骤,并在实际验证中取得了良好的效果.     

WCDMA/HSDPA系统中的Turbo译码器设计与优化

Turbo码由于其优越的性能正日益广泛应用到移动、卫星和深空通信系统中。以Turbo译码器的ASIC实现为目标,介绍了它在WCDMA/HSDPA系统中的实际应用,对其算法、实现复杂度进行了分析,对常规扩充结构进行了优化,减少了面积和功耗,减少不必要的运算开支,节约了芯片成本,提高了产品竞争力。     

A Low Power Dissipation Technique for a Low Voltage OTA

This paper proposes a novel low power dissipation technique for a low voltage OTA. A conventional low power OTA with a class AB input stage is not suitable for a low voltage operation (±1.5 V supply voltages), because it uses composite transistors (referred to CMOS pair) which has a large threshold voltage. On the other hand, the tail-current type OTA needs a large tail-current value to obtain a sufficient input range at the expense of power dissipation. Therefore, the conventional tail-current type OTA has a trade-off between the input range and the power dissipation to the tail-current value. The trade-off can be eliminated by the proposed technique. The technique exploits negative feedback control including a current amplifier and a minimum current selecting circuit. The proposed technique was used on Wang's OTA to create another OTA, named Low Power Wang's OTA. Also, SPICE simulations are used to verify the efficiency of Low Power Wang's OTA. Although the static power of Low Power Wang's OTA is 122 W, it has a sufficient input range, whereas conventional Wang's OTA needs 703 W to obtain a sufficient input range. However, we can say that as the input signal gets larger, the power of Low Power Wang's OTA becomes larger.     

A New Unequal Power Allocation Scheme for Asymmetric Turbo Code System

In this paper, a modified unequal power allocation scheme for the different bits of asymmetric turbo encoder has been investigated to enhance the performance. The simulation results and performance bound for the asymmetric turbo code with modified Unequal Power Allocation (UPA) scheme are obtained and compared with the system with typical UPA and without UPA. From the performance results, it is observed that the proposed asymmetric turbo code with modified UPA performs better than the system without UPA and with typical UPA and it provides a coding gain of 0.4–0.52 dB.

X波段便携式战场侦察雷达收发系统低功耗设计

便携式战场侦察雷达具有低截获、高灵敏度、结构灵巧、发射功率小、架拆迅速、配置人员少等特点,其不仅适用于战场前沿,也适用于和平时期的很多场合,因此越来越被人们关注。收发系统作为便携式战场侦察雷达的重要组成部分,其功耗为工程设计的重点。便携式战场侦察雷达收/发系统的设计主要任务是在符合整机指标的前提下,如何降低功耗、体积、重量。本文论述了一种便携式战场侦察雷达收/发系统低功耗设计技术,经测试该系统功耗小于20W     

卫星移动通信终端的低功耗设计

低功耗设计是电子产品设计的重要环节,特别是对工作在野外环境的卫星移动通信手持终端类产品而言,低功耗设计是延长终端待机时间和使用寿命的重要途径。在对通信产品整机及各类组成单元功耗产生原理分析的基础上,分别从整机、单元电路、主要元器件及FPGA代码设计等几个方面入手,讨论了采用通用元器件设计的卫星通信终端的低功耗设计方法,并给出了改进设计后的低功耗设计效果。     

Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications

In this paper, we address the issues of designing lowpower VLSI implementation of the Code DivisionMultiple Access (CDMA) receiver. Among all the digitalfunctional blocks of a CDMA receiver, the RAKEreceiver and the Viterbi decoder are the mostcomputational intensive and hence consume most of thepower. In this work, we propose new VLSI architecturesfor these two functional blocks which consumesignificantly lower power. In particular, were-organize the structure of the pilot-aided RAKEdemodulator to reduce the operational frequency of thearithmetic components and we propose a newAdd-Compare-Select (ACS) architecture for the Viterbidecoder which can reduce the complexity of thecomputation. Also a novel pre-computationalarchitecture is proposed to further reduce the powerconsumption of the ACS unit. Experimental results showsignificant reduction in power consumption.