Surface and electrical properties of organic-inorganic hybrid structure as gate insulator to organic thin film transistor

Carbon-based OTFT devices were fabricated using a plasma process for the gate electrode and gate insulators. A nanocrystalline carbon (nc-C) film was used as the gate electrode, and three different layers, cyclohexene, diamond-like carbon (DLC), and cyclohexene/DLC (hybrid insulator), were used as the gate insulator. The surface and electrical properties of the three different gate insulators on the nc-C gate electrode were investigated using the SPM method, and the leakage current density and dielectric constant of the metal-insulator-metal (MIM) structures with three different insulator layers were evaluated. The hybrid insulator layer had a very smooth surface, approximately 0.2 nm, a uniform surface without defects, and good adhesion between the layers. Overall, it is believed that the hybrid insulator lead to a decrease in the electrical leakage current and an improvement in the device performance.     

N2O Plasma表面处理对SiNx基IGZO-TFT性能的影响

采用N₂O plasma处理SiN_x薄膜作为绝缘层,以室温下沉积的铟镓锌氧化物(IGZO)作为有源层制备了 IGZO薄膜晶体管。与常规的IGZO-TFT相比,N₂O plasma处理过的IGZO-TFT的迁移率由原来的4.5 cm²·V^-1·s^-1增 加至8.1 cm²·V^-1·s^-1,阈值电压由原来的11.5 V减小至3.2 V,亚阈值摆由原来的1.25 V/decade减小至0.9 V/decade。采用C-V方法计算了两种器件的陷阱态,结果发现N₂O plasma处理过的IGZO-TFT的陷阱态明显小于普通的IGZO-TFT的陷阱态,表明N₂O plasma处理SiN_x绝缘层是一种改善IGZO-TFT器件性能的有效方法。     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Al_2O_3薄层修饰SiN_x绝缘层的IGZO-TFTs器件的性能研究

采用原子层沉积工艺(ALD)生长均匀致密的三氧化二铝(Al2O3)薄层对氮化硅(Si Nx)绝缘层进行修饰,研究了铟镓锌氧薄膜晶体管(IGZO-TFTs)器件的性能。当Al2O3修饰层厚度为4 nm时,绝缘层-有源层界面的最大缺陷态密度相比于未修饰器件降低了17.2%,器件性能得到显著改善。场效应迁移率由1.19 cm2/(V·s)提高到7.11 cm2/(V·s),阈值电压由39.70 V降低到25.37 V,1 h正向偏压应力下的阈值电压漂移量由2.19 V减小到1.41 V。     

Organic insulator layer influence on the electrical properties of N,N’-di (2-ethylhexyl) - 3, 4, 9, 10-perylene diimide organic thin-film transistors: Experiment and modeling

In this work, n- type organic thin film transistors (OTFTs) based on different kinds of organic dielectrics were fabricated, characterized and theoretically investigated. Three kinds of organic insulators were applied as dielectric gate which are: divinyl tetramethyl disiloxane-bis (benzo-cyclobutene) (BCB), poly(vinylalcohol) (PVA) and poly (4-vinyl phenol) (PVP). Analytical model was applied to describe the electrical behavior of the fabricated OTFTs and to explain the absence of saturation of the drain current for the device based on PVA dielectric. In addition, Meyer–Neldel rule-grain boundary model was applied for the calculation of total resistance of OTFTs based on different dielectrics materials. The theoretical results of output characteristics and total resistance showed an excellent agreement with the experimental measurements. The experimental and theoretical calculations revealed that the n-channel OTFTs based on BCB as an insulator layer exhibited superior electrical characteristics in terms of threshold voltage, mobility and drain current compared with the devices based on PVA and PVP as a gate insulator layer. The device based on BCB organic insulator layer has the largest mobility of 4?×?10^?3 cm² V^?1 s^?1, the smallest leakage current relative to the devices based on PVA and PVP. While, the device fabricated with PVP organic insulator gate has a large trap density on the PVP-EHPDI interface which causes a pronounced decrease in field effect mobility and consequently drain current.     

具有高开启/关断电流比的Al2O3/AlGaN/GaN金属氧化物半导体高电子迁移率晶体管

采用原子层淀积(ALD)方法,制备了Al₂O₃为栅介质的高性能AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT)。在栅压为-20 V时,MOS-HEMT的栅漏电比Schottky-gate HEMT的栅漏电低4个数量级以上。在栅压为+2 V时,Schottky-gate HEMT的栅漏电为191μA;在栅压为+20 V时,MOS-HEMT的栅漏电仅为23.6 nA,比同样尺寸的Schottky-gate HEMT的栅漏电低将近7个数量级。AlGaN/GaN MOS-HEMT的栅压摆幅达到了±20 V。在栅压V_gs=0 V时, MOS-HEMT的饱和电流密度达到了646 mA/mm,相比Schottky-gate HEMT的饱和电流密度(277 mA/mm)提高了133%。栅漏间距为10μm的AlGaN/GaN MOS-HEMT器件在栅压为+3 V时的最大饱和输出电流达到680 mA/mm,特征导通电阻为1.47 mΩ·cm²。Schottky-gate HEMT的开启与关断电流比仅为10⁵,MOS-HEMT的开启与关断电流比超过了10⁹,超出了Schottky-gate HEMT器件4个数量级,原因是栅漏电的降低提高了MOS-HEMT的开启与关断电流比。在V_gs=-14 V时,栅漏间距为10μm的AlGaN/GaN MOS-HEMT的关断击穿电压为640 V,关断泄露电流为27μA/mm。     

Spin-polarized tunneling in a ferromagnetic graphene junction: Interplay between the exchange interaction and the orbital effect of the magnetic field

The influence of magnetic vector potential barrier (MVPB) on the spin-polarized transport of massless Dirac particles in ferromagnetic graphene is studied theoretically. The phenomenon of Klein tunneling of relativistic particles across a rectangular potential barrier prevents any of the massless fermions from being confined but they can be electrically confined by quantum dots with integrable dynamics (Bardarson et al., 2009) [36]. Utilization of only the in-plane exchange splitting in the ferromagnetic graphene cannot produce 100% spin polarization. This tunneling can be confined using the magnetic vector potential barrier, which leads to high degree of spin polarization. By combining the orbital effect and the Zeeman interaction in graphene junction, it is found that the junction mimics behavior of half-metallic tunneling junction, in which it acts as a metal to particles of one spin orientation but as an insulator or a semiconductor to those of the opposite orientation. The idea of the half-metallic tunneling junction can provide a source of ∼100% spin-polarized current, which is potentially very useful. Adjustment of the position of the Fermi level in ferromagnetic layer by placing a gate voltage on top of the ferromagnetic layer shows that reverse of the orientation of the completely spin-polarized current passing through the junction is controlled by adjusting the gate voltage. These interesting characteristics should lead to a practical gate voltage controlled spin filtering and spin-polarized switching devices as a perfect spin-polarized electron source for graphene-based spintronics.     

Influence of charge deposition in a field-emission display panel

Field-emission displays (FEDs) have been studied intensively in recent years as a candidate for flat-display panels in the future. In a FED, electrons emit from field emitters. Some electrons may impinge on the insulator surface between cathode and gate electrodes and cause charging of that surface because the yield of secondary electron emission is usually not equal to one. The charging of the insulator walls between cathode and gate electrodes is one of the important factors influencing the performance of a FED. In this paper, a simulation program is used to calculate this charge deposition, electric field distribution and electron trajectories. From the change of the electric field upon charge deposition in the triode region, it is shown that the insulator surface is negatively charged at a low gate voltage, e.g. 20 V. However, positive charge is deposited when the gate voltage is high, e.g. 100 V. The simulations also show that the emission current will increase even further after coating the dielectric with a thin film of a material with a high-secondary emission coefficient such as MgO. If a cone-shaped dielectric aperture is used in a triode, the emission current will decrease after charge deposition. However, the focus performance of the electron beam is improving in this case.     

Photo-curable epoxy functionalized cyclotetrasiloxane as a gate dielectric for organic thin film transistors

We synthesized a new photo-curable organic/inorganic hybrid material, cyclotetrasiloxane (CTS) derivative containing cyclohexene-1,2-epoxide functional groups (CTS-EPOXY), and its characteristics are compared with a prototypical organic gate insulator of poly(4-vinylphenol) (PVP) in the organic thin film transistors (OTFTs) using pentacene as an active p-type organic semiconductor. Compared with PVP, CTS-EPOXY shows better insulating characteristics and surface smoothness. A metal/insulator/metal (MIM) device with the 300-nm-thick CTS-EPOXY film shows more than two orders of magnitude lower current (less than 40 nA/cm² over the voltage range up to 60 V) compared with PVP. In addition, the pentacene TFT with CTS-EPOXY as a gate dielectric layer shows slightly higher field-effect mobility of μ_FET = 0.20 cm²/V s compared to that with PVP.     

不同绝缘层上生长的并五苯薄膜及其OTFT器件性能的研究

分别以SiO₂和PMMA为绝缘层材料制备了底栅顶接触结构的OTFT器件,得到以PMMA为绝缘层的器件具有更好的性能,其场效应迁移率为0.207 cm2·Vs-1,开关电流比为4.93×103,阈值电压为-4.3 V;而以SiO₂为绝缘层的器件,其场效应迁移率仅为0.039 cm2·Vs-1,开关电流比为5.98×102,阈值电压为-5.4 V。为分析器件性能差异的原因,测得了SiO₂和PMMA薄膜表面的AFM图谱及其上沉积并五苯薄膜后的AFM和XRD图谱。通过AFM图谱发现PMMA表面较SiO₂表面粗糙度小,其表面粗糙度的均方根值为0.216 nm,而二氧化硅薄膜表面粗糙度的均方根值为1.579 nm;且发现在PMMA上生长的并五苯薄膜的成膜质量优于在SiO₂,具有较大的晶粒尺寸和较少的晶粒间界。通过XRD图谱发现在PMMA上生长的并五苯薄膜具有明显的衍射峰,进一步证明了在PMMA上生长的并五苯薄膜具有更好的结晶状况,将更有利于载流子的传输。     

Normally-off AlGaN/GaN heterojunction field-effect transistors with in-situ AlN gate insulator

AlGaN/GaN heterojunction field-effect transistors (HFETs) with p-GaN cap layer are developed for normally-off operation, in which an in-situ grown AlN layer is utilized as the gate insulator. Compared with the SiN_x gate insulator, the AlN/p-GaN interface presents a more obvious energy band bending and a wider depletion region, which helps to positively shift the threshold voltage. In addition, the relatively large conduction band offset of AlN/p-GaN is beneficial to suppress the gate leakage current and enhance the gate breakdown voltage. Owing to the introduction of AlN layer, normally-off p-GaN capped AlGaN/GaN HFET with a threshold voltage of 4 V and a gate swing of 13 V is realized. Furthermore, the field-effect mobility is approximately 1500 cm²·V^-1·s^-1 in the 2DEG channel, implying a good device performance.     

Low-voltage-drive and high output current ZnO thin-film transistors with sputtering SiO2 as gate insulator

Low-voltage-drive ZnO thin-film transistors (TFTs) with room-temperature radio frequency magnetron sputtering SiO₂ as the gate insulator were fabricated successfully on the glass substrate. The ZnO-TFT operates in the enhancement mode with a threshold voltage of 4.2 V, a field effect mobility of 11.2 cm²/V s, an on/off ratio of 3.1 × 10⁶ and a subthreshold swing of 0.61 V/dec. The drain current can reach to 1 mA while the gate voltage is only of 12 V and drain voltage of 8 V. The C–V characteristics of a MOS capacitor with the structure of ITO/SiO₂/ZnO/Al was investigated. The carrier concentration N_D in the ZnO active layer was determined, the calculated N_D is 1.81 × 10¹⁶ cm⁻³, which is the typical value of undoped ZnO film used as the channel layer for ZnO-TFT devices. The experiment results show that SiO₂ film is a promising insulator for the low voltage and high drive capability oxide TFTs.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

Ta2O5-PMMA复合栅绝缘层对OFETs性能的影响

选用五氧化二钽（Ta₂O₅）-聚甲基丙烯酸甲酯（PMMA）复合材料作为栅绝缘层制备了并五苯有机场效应晶体管（OFETs）。通过在Ta₂O₅表面旋涂一层PMMA可以降低栅绝缘层的表面粗糙度,增大其场效应晶体管的迁移率。研究了厚度在20~60 nm范围内的PMMA对复合绝缘层表面形貌、粗糙度以及器件电学性能的影响。结果表明,当PMMA厚度为40 nm时,器件的电学性能最佳。与单一的Ta₂O₅栅绝缘层器件相比,其场效迁移率由4.2×10^-2 cm²/（V·s）提高到0.31 cm²/（V·s）;栅电压增加到-20 V时,开关电流比由2.9×10²增大到2.9×10⁵。     

InGaZnO薄膜晶体管背板的栅极驱动电路静电释放失效研究

本文通过解析阵列基板栅极驱动(gate driver on array, GOA)电路中发生静电释放(electro-static discharge,ESD)的InGaZnO薄膜晶体管(InGaZnO thin-film transistor, IGZO TFT)器件发现:栅极Cu金属扩散进入了SiN_x/SiO_2栅极绝缘层;源漏极金属层成膜前就发生了ESD破坏;距离ESD破坏区域越近的IGZO TFT,电流开关比越小,直到源漏极与栅极完全短路.本文综合IGZO TFT器件工艺、GOA区与显示区金属密度比、栅极金属层与绝缘层厚度非均匀性分布等因素,采用ESD器件级分析与系统级分析相结合的方法,提出栅极Cu:SiN_x/SiO_2界面缺陷以及这三层薄膜的厚度非均匀分布是导致GOA电路中沟道宽长比大的IGZO TFT发生ESD失效的关键因素,并针对性地提出了改善方案.     

同步对称双栅InGaZnO薄膜晶体管电势模型研究

研究了同步对称双栅氧化铟镓锌薄膜晶体管(InGaZnO thin film transistors,IGZO TFTs)的沟道电势,利用表面电势边界方程联合Lambert函数推导得到了器件沟道电势的解析模型.该模型考虑了IGZO薄膜中存在深能态及带尾态等缺陷态密度,能够同时精确地描述器件在亚阈区(sub-threshold)与开启区(above threshold)的电势分布.基于所提出的双栅IGZO TFT模型,讨论了不同厚度的栅介质层和有源层时,栅-源电压对双栅IGZO TFT的表面势以及中心势的调制效应.对比分析了该模型的计算值与数值模拟值,结果表明二者具有较高的符合程度.     

高跨导氢终端多晶金刚石长沟道场效应晶体管特性研究

基于多晶金刚石制作了栅长为4 pm的铝栅氢终端金刚石场效应晶体管.器件的饱和漏源电流为160 mA/mm,导通电阻低达37.85Ω·mm,最大跨导达到32 mS/mm,且跨导高于最大值的90%的栅压(V_(GS))范围达到3 V(-2 V≤V_(GS)≤-5 V).通过传输线电阻分析以及器件的导通电阻和电容-电压特性分析,发现氢终端多晶金刚石栅下沟道中的空穴面浓度达到了1.56×10~(13)cm~(-2),有效迁移率在前述高跨导栅压范围保持在约170 cm~2/(V·s).分析认为,较低的栅源和栅漏串联电阻、沟道中高密度的载流子和在大范围栅压内的高水平迁移率是引起高而宽阔的跨导峰和低导通电阻的原因.     

An AlGaN/GaN HEMT with enhanced breakdown and near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is experimentally verified. The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain. When compared to a similar size HEMT device with conventional field plate (CFP) structure, the AFP not only minimizes the parasitic gate to source capacitance, but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm, three times higher forward blocking voltage of 375 V was obtained at V_GS=-5 V. In contrast, a similar sized HEMT with CFP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. Moreover, a temperature coefficient of 0 V/K for the breakdown voltage is observed. However, devices without field plate (no FP) and with optimized conventional field plate (CFP) exhibit breakdown voltage temperature coefficients of -0.113 V/K and -0.065 V/K, respectively.     

Use of negative capacitance to simulate the electrical characteristics in double-gate ferroelectric field-effect transistors

The surface potential and drain current of double-gate metal-ferroelectric-insulator-semiconductor (MFIS) field-effect transistor were investigated by using the ferroelectric negative capacitance. The derived results demonstrated that the up-converted semiconductor surface potential and low subthreshold swing S = 34 (<60 mV/dec) can be realized with appropriate thicknesses of ferroelectric thin film and insulator layer at room temperature. What's more, a reduction gate voltage about 260 mV can be reached if the ON-state current is fixed to 600 μA/μm. It is expected that the derived results can offer useful guidelines for the application of low power dissipation in ongoing scaling of FETs.