Partial-SOI high voltage P-channel LDMOS with interface accumulation holes

A new partial SOI (silion-on-insulator) (PSOI) high voltage P-channel LDMOS (lateral double-diffused metal-oxide semiconductor) with an interface hole islands (HI) layer is proposed and its breakdown characteristics are investigated theoretically. A high concentration of charges accumulate on the interface, whose density changes with the negative drain voltage, which increase the electric field (E_I) in the dielectric buried oxide layer (BOX) and modulate the electric field in drift region . This results in the enhancement of the breakdown voltage (BV). The values of E_I and BV of an HI PSOI with a 2-μm thick SOI layer over a 1-μm thick buried layer are 580V/μm and -582 V, respectively, compared with 81.5 V/μm and -123 V of a conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect (SHE). Moreover, in comparison with the conventional device, the proposed device exhibits low on-resistance.     

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator (PSOI) high voltage device with a low-k (relative permittivity) dielectric buried layer (LK PSOI) and its breakdown mechanism are presented and investigated by MEDICI.At a low k value the electric field strength in the dielectric buried layer (E I) is enhanced and a Si window makes the substrate share the vertical drop,resulting in a high vertical breakdown voltage;in the lateral direction,a high electric field peak is introduced at the Si window,which modulates the electric field distribution in the SOI layer;consequently,a high breakdown voltage (BV) is obtained.The values of EI and BV of LK PSOI with kI=2 on a 2 μm thick SOI layer over 1 μm thick buried layer are enhanced by 74% and 19%,respectively,compared with those of the conventional PSOI.Furthermore,the Si window also alleviates the self-heating effect.     

Novel high-voltage power lateral MOSFET with adaptive buried electrodes

A new high-voltage and low-specific on-resistance (R on,sp ) adaptive buried electrode (ABE) silicon-on-insulator (SOI) power lateral MOSFET and its analytical model of the electric fields are proposed. The MOSFET features are that the electrodes are in the buried oxide (BOX) layer, the negative drain voltage V d is divided into many partial voltages and the output to the electrodes is in the buried oxide layer and the potentials on the electrodes change linearly from the drain to the source. Because the interface silicon layer potentials are lower than the neighboring electrode potentials, the electronic potential wells are formed above the electrode regions, and the hole potential wells are formed in the spacing of two neighbouring electrode regions. The interface hole concentration is much higher than the electron concentration through designing the buried layer electrode potentials. Based on the interface charge enhanced dielectric layer field theory, the electric field strength in the buried layer is enhanced. The vertical electric field E I and the breakdown voltage (BV) of ABE SOI are 545 V/μm and -587 V in the 50 μm long drift region and the 1 μm thick dielectric layer, and a low R on,sp is obtained. Furthermore, the structure also alleviates the self-heating effect (SHE). The analytical model matches the simulation results.     

A-188 V 7.2Ω·mm~2,P-channel high voltage device formed on an epitaxy-SIMOX substrate

This paper proposes a new n +-charge island (NCI) P-channel lateral double diffused metal-oxide semiconductor (LDMOS) based on silicon epitaxial separation by implantation oxygen (E-SIMOX) substrate.Higher concentration self-adapted holes resulting from a vertical electric field are located in the spacing of two neighbouring n +-regions on the interface of a buried oxide layer,and therefore the electric field of a dielectric buried layer (E I) is enhanced by these holes effectively,leading to an improved breakdown voltage (BV).The V B and E I of the NCI P-channel LDMOS increase to-188 V and 502.3 V/μm from 75 V and 82.2 V/μm of the conventional P-channel LDMOS with the same thicknesses SOI layer and the buried oxide layer,respectively.The influences of structure parameters on the proposed device characteristics are investigated by simulation.Moreover,compared with the conventional device,the proposed device exhibits low special on-resistance.     

Novel high-voltage power device based on self-adaptive interface charge

This paper presents a novel high-voltage lateral double diffused metal--oxide semiconductor (LDMOS) with self-adaptive interface charge (SAC) layer and its physical model of the vertical interface electric field. The SAC can be self-adaptive to collect high concentration dynamic inversion holes, which effectively enhance the electric field of dielectric buried layer (E_I) and increase breakdown voltage (BV). The BV and E_I of SAC LDMOS increase to 612 V and 600 V/μm from 204 V and 90.7 V/μm of the conventional silicon-on-insulator, respectively. Moreover, enhancement factors of η which present the enhanced ability of interface charge on E_I are defined and analysed.     

A new structure and its analytical model for the vertical interface electric field of a partial-SOI high voltage device

A new partial-SOI (PSOI) high voltage device structure called a CI PSOI (charge island PSOI) is proposed for the first time in this paper. The device is characterized by a charge island layer on the interface of the top silicon layer and the dielectric buried layer in which a series of equidistant high concentration n⁺-regions is inserted. Inversion holes resulting from the vertical electric field are located in the spacing between two neighbouring n⁺-regions on the interface by the force with ionized donors in the undepleted n⁺-regions, and therefore effectively enhance the electric field of the dielectric buried layer (E_I) and increase the breakdown voltage (BV), thereby alleviating the self-heating effect (SHE) by the silicon window under the source. An analytical model of the vertical interface electric field for the CI PSOI is presented and the analytical results are in good agreement with the 2D simulation results. The BV and E_I of the CI PSOI LDMOS increase to 631~V and 584~V/μ m from 246~V and 85.8~V/μ m for the conventional PSOI with a lower SHE, respectively. The effects of the structure parameters on the device characteristics are analysed for the proposed device in detail.     

Ultra-low on-resistance high voltage (>600 V) SOI MOSFET with a reduced cell pitch

A low specific on-resistance (R S,on) silicon-on-insulator (SOI) trench MOSFET (metal-oxide-semiconductor-field-effect-transistor) with a reduced cell pitch is proposed.The lateral MOSFET features multiple trenches:two oxide trenches in the drift region and a trench gate extended to the buried oxide (BOX) (SOI MT MOSFET).Firstly,the oxide trenches increase the average electric field strength along the x direction due to lower permittivity of oxide compared with that of Si;secondly,the oxide trenches cause multiple-directional depletion,which improves the electric field distribution and enhances the reduced surface field (RESURF) effect in the SOI layer.Both of them result in a high breakdown voltage (BV).Thirdly,the oxide trenches cause the drift region to be folded in the vertical direction,leading to a shortened cell pitch and a reduced R S,on.Fourthly,the trench gate extended to the BOX further reduces R S,on,owing to the electron accumulation layer.The BV of the MT MOSFET increases from 309 V for a conventional SOI lateral double diffused metal-oxide semiconductor (LDMOS) to 632 V at the same half cell pitch of 21.5 μm,and R S,on decreases from 419 m · cm 2 to 36.6 m · cm 2.The proposed structure can also help to dramatically reduce the cell pitch at the same breakdown voltage.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator (NFL SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and the NFL-assisted modulated field (NFLAMF) principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer (BOX). At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage (BV) is increased from 315 V to 558 V compared to the conventional reduced surface field (RESURF) SOI (CSOI) LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.     

Improvement of total-dose irradiation hardness of silicon-on-insulator materials by modifying the buried oxide layer with ion implantation

The hardening of the buried oxide (BOX) layer of separation by implanted oxygen (SIMOX) silicon-on-insulator (SOI) wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad(SiO₂. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.     

Novel approaches for low cost fabrication of SOI

Two trials for low cost manufacture of silicon-on-insulator (SOI) wafers were implemented. Low dose separation by implantation of oxygen (SIMOX) procedure has been conducted on a beam-line ion implanter with mass analyzer. The energy dependence of the formed SOI structure was studied at varied implant dosages. The integrity of the buried oxide (BOX) layer was examined by transmission electron microscopy (TEM) and the threading dislocation in the top silicon layer was evaluated by Secco technique. The results indicated that not only the implanted oxygen dose but also the oxygen ion energy plays an important role in the formation of SOI structure with good crystallinity of top silicon, sharp Si/SiO₂ interfaces and highly integrated BOX layer free of silicon inclusion. For separation by plasma implantation of oxygen (SPIMOX) approach, water plasma, rather than oxygen plasma, was employed to avoid oxygen spread in the implant depth profile. The SPIMOX process using water plasma was carried out on a beam-line ion implanter without mass selector to simulate the plasma implantation procedure. Cross-sectional TEM study revealed that uniform BOX layer was formed under single crystal silicon superficial layer with the present approach. The interfaces between silicon superficial layer, BOX layer and bulk silicon were smooth and sharp. An implant dose window has been identified for fabricating the desirable SOI structure.     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

A high voltage silicon-on-insulator lateral insulated gate bipolar transistor with a reduced cell-pitch

A high voltage( 600 V) integrable silicon-on-insulator(SOI) trench-type lateral insulated gate bipolar transistor(LIGBT) with a reduced cell-pitch is proposed.The LIGBT features multiple trenches(MTs):two oxide trenches in the drift region and a trench gate extended to the buried oxide(BOX).Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field(RESURF) effect.Both increase the breakdown voltage(BV).Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop(Von).The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss(Eoff).The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10?3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.     

A novel P-channel SOI LDMOS structure with non-depletion potential-clamped layer

A novel structure is proposed for doubling the vertical breakdown voltage of silicon-on-insulator(SOI) devices. In this new structure, the conventional buried oxide(BOX) in an SOI device is split into two sections: the source-section BOX and the drain-section BOX. A highly-doped Si layer, referred to as a non-depletion potential-clamped layer(NPCL), is positioned under and close to the two BOX sections. In the split BOXes and the Si region above the BOXes, the blocking voltage(BV) is divided into two parts by the NPCL. The voltage in the NPCL is clamped to be nearly half of the drain voltage. When the drain voltage approaches a breakdown value, the voltage sustained by the source-section BOX and the Si region under the source are nearly the same as the voltage sustained by the drain-section BOX and the Si region under the drain. The vertical BV is therefore almost doubled. The effectiveness of this new structure was verified for a P-channel SOI lateral double-diffused metal-oxide semiconductor(LDMOS) and can be applied to other high-voltage SOI devices. The simulation results show that the BV in an NPCL P-channel SOI LDMOS is improved by 55% and the specific on-resistance(Ron,sp) is reduced by 69% in comparison to the conventional structure.     

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) n-channel lateral double-diffused metal-oxide-semiconductor(LDMOS) is proposed and its mechanism is investigated by simulation.The LDMOS has two features:the integration of a planar gate and an extended trench gate(double gates(DGs));and a buried P-layer in the N-drift region,which forms a triple reduced surface field(RESURF)(TR) structure.The triple RESURF not only modulates the electric field distribution,but also increases N-drift doping,resulting in a reduced specific on-resistance(Ron,sp) and an improved breakdown voltage(BV) in the off-state.The DGs form dual conduction channels and,moreover,the extended trench gate widens the vertical conduction area,both of which further reduce the Ron,sp.The BV and Ron,sp are 328 V and 8.8 m.cm2,respectively,for a DG TR metal-oxide-semiconductor field-effect transistor(MOSFET) by simulation.Compared with a conventional SOI LDMOS,a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%.The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit,thereby saving the chip area and simplifying the fabrication processes.     

新型SOANN埋层SOI器件的自加热效应研究

本文提出了一个新型的SOI埋层结构SOANN (silicon on aluminum nitride with nothing),用AlN代替传统的SiO₂材料,并在SOI埋氧化层中引入空洞散热通道. 分析了新结构SOI器件的自加热效应.研究结果表明:用AlN做为SOI埋氧化层的材料, 降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道, 使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合, 有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.     

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator(SOI) high breakdown voltage(BV) power device with interlaced dielectric trenches(IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges(holes) at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.     

Compound buried layer SOI high voltage device with a step buried oxide

A silicon-on-insulator (SOI) high performance lateral double-diffusion metal oxide semiconductor (LDMOS) on a compound buried layer (CBL) with a step buried oxide (SBO CBL SOI) is proposed.The step buried oxide locates holes in the top interface of the upper buried oxide (UBO) layer.Furthermore,holes with high density are collected in the interface between the polysilicon layer and the lower buried oxide (LBO) layer.Consequently,the electric fields in both the thin LBO and the thick UBO are enhanced by these holes,leading to an improved breakdown voltage.The breakdown voltage of the SBO CBL SOI LDMOS increases to 847 V from the 477 V of a conventional SOI with the same thicknesses of SOI layer and the buried oxide layer.Moreover,SBO CBL SOI can also reduce the self-heating effect.     

Silicon-on-insulator microcavity light emitting diodes with two Si/SiO2 Bragg reflectors

Light emitting pn-diodes were fabricated on a 5.8 μm thick n-type Si device layer of a silicon-on-insulator (SOI) wafer using standard silicon technology and boron implantation. The thickness of the Si device layer was reduced to 1.3 μm, corresponding to a 4λ-cavity for λ=1150 nm light. Electroluminescence spectra of these low Q-factor microcavities are presented. Addition of Si/SiO₂ Bragg reflectors on the top and bottom of the device (3.5 and 5.5 pairs, respectively) is predicted to lead to spectral emission enhancement by ∼270.     

New SOI power device with multi-region high-concentration fixed interface charge and the model of breakdown voltage

A new SOI power device with multi-region high-concentration fixed charge(MHFC) is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer(BOX), by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.