On-chip matched 5.2 and 5.8 GHz differential LNAs fabricated using0.35 μm CMOS technology

The authors have designed experimental 5.2 and 5.8 GHz low-noise amplifiers (LNAs) using 0.35 μm CMOS technology. The ICs feature on-chip matching to 50 Ω, differential operation, and open drain output buffers. A return loss of better than -15 dB was achieved for both amplifiers. LC parallel resonant loads were used to form the gain peak. The LNAs had a measured noise figure of 4 to 5 dB, at VSS=3.3 V     

A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 μm technology and applied to 0.13 μm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

Low-temperature characteristics of 0.35 μm AlSb/InAs HEMTs

The effects of low temperature on the characteristics of 0.35 μm gate-length AlSb/InAs HEMTS are reported. Measurements down to 15 K reveal an increase in transconductance and low-field source-drain conductance. The commonly-observed impact ionisation and its associated gate current were found to decrease significally at low temperature apparently due to a increase in bandgap     

A manufacturing sensitivity analysis of 0.35 μm LDD MOSFET's

Fundamental to successful manufacturing of integrated circuits is the achievement of sufficient control in all process steps to realize, with very high yield, fully functional circuits whose performance and reliability conform to pre-determined standards. Towards this end, it is increasingly necessary to relate in a quantitative manner the sensitivity of the electrical performance of the final devices and circuits to variations in structural parameters and doping profiles, which in turn can be related to process and tool performance variations. In this paper, we describe the results of an analysis performed to quantify the sensitivity of the electrical parameters of a 0.35 μm LDD MOSFET to variations in the doping and structural parameters of the device that are anticipated in manufacturing. A central-composite design was used to develop second-order models for six key device electrical parameters. The resulting models are manifested as second-order equations relating the device electrical parameter variations to random variations in seven key device structure and doping parameters. This set of equations thus allows one to understand quantitatively the source and nature of the device electrical parameter variations. A simple Monte Carlo approach is applied to predict the statistical distributions of the key device electrical parameters which result from the random manufacturing variations in the structure and doping parameters by using the quantitative relationships developed in this paper     

6.8 GHz monolithic oscillator fabricated by 0.35 μm CMOStechnologies

A 6.8 GHz CMOS monolithic oscillator with a 5.9 dBm output power has been demonstrated by 0.35 μm 1P4M CMOS technologies. The oscillator was designed based on a home-made modified BSIM3v3 large-signal model, where the high-frequency parasitics were included. In addition, on chip spiral inductors and MIM capacitors for the resonant circuit were characterised and used in this monolithic oscillator circuit     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

Optimization of implant anneals to improve transistor performancein a 0.15 μm CMOS technology

The impact of including a rapid thermal anneal step after the extension implants is examined for a 0.15 μm CMOS process. SIMS data will verify that shallower junctions can be obtained with only a single anneal cycle after the source-drain implants, implying that transient enhanced diffusion is minimal for this technology. Further, transistor data indicates that improved CMOS device performance can be obtained without the extension anneal cycle     

A family of low-power truly modular programmable dividers instandard 0.35-μm CMOS technology

A truly modular and power-scalable architecture for low-power programmable frequency dividers is presented. The architecture was used in the realization of a family of low-power fully programmable divider circuits, which consists of a 17-bit UHF divider, an 18-bit L-band divider, and a 12-bit reference divider. Key circuits of the architecture are 2/3 divider cells, which share the same logic and the same circuit implementation. The current consumption of each cell can be determined with a simple power optimization procedure. The implementation of the 2/3 divider cells is presented, the power optimization procedure is described, and the input amplifiers are briefly discussed. The circuits were processed in a standard 0.35 μm bulk CMOS technology, and work with a nominal supply voltage of 2.2 V. The power efficiency of the UHF divider is 0.77 GHz/mW, and of the L-band divider, 0.57 GHz/mW. The measured input sensitivity is >10 mV rms for the UHF divider, and >20 mV rms for the L-band divider     

New Ti-SALICIDE process using Sb and Ge preamorphization forsub-0.2 μm CMOS technology

A new process for thin titanium self-aligned silicide (Ti-SALICIDE) on narrow n⁺ poly-Si lines and n⁺ diffusion layers using preamorphization implantation (PAI) with heavy ions of antimony (Sb) and germanium (Ge) has been demonstrated for application to 0.2-μm CMOS devices and beyond. Preamorphization enhances the phase transformation from C₄₉Ti_xSi _x to C₅₄TiSi₂ and lowers the transformation temperature by 80°C so that it occurs before conglomeration in narrow lines. Preamorphization by Sb and Ge implantation yields better results than that by As. The sheet resistance of TiSi₂ on heavily As doped poly-Si lines are 3.7 Ω/□ and 3.8 Ω/□ for the samples preamorphized by Ge and Sb implantations even with line width down to 0.2 μm. There is less leakage in the Ti-SALICIDE diode with preamorphization than without it. The probable reasons and mechanisms are discussed     

350 MHz opamp-RC filter in 0.18 μm CMOS

A 350 MHz fifth-order elliptic opamp-RC filter demonstrates that opamp-based filters need not have bandwidth disadvantages compared to transconductor-based filters. The filter, fabricated in standard digital 0.18 μm CMOS with 1.8 V V_DD, achieves 0.5 Vp-p signal swing at -40 dB THD     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

A low-voltage CMOS complementary active pixel sensor (CAPS)fabricated using a 0.25 μm CMOS technology

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a V_DD below 1 V with a reasonable output swing     

On-chip characterization of interconnect parameters and time delayin 0.18 μm CMOS technology for ULSI circuit applications

A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 μm CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 μm to the 0.18 μm technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

2 Gbit/s transimpedance amplifier fabricated by 0.35 μm CMOStechnologies

Integrated CMOS transimpedance (TZ) amplifier circuits have been designed and fabricated based on a home-made BSIM model. A 0.35 μm CMOS technology was used for circuit realisation, and a capacitive-peaking design to improve the bandwidth of the TZ amplifier is proposed and investigated. Using this approach provides an easy way to improve the performance of the TZ amplifier; the measured 3 dB bandwidth is enhanced from 875 MHz to 1.35 GHz. The CMOS TZ amplifier design achieves a 2 Gbit/s data rate     

Inverter performance of 0.10 μm CMOS operating at roomtemperature

The switching performance of 0.10 μm CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 μm gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 μm CMOS. The switching performance of a 0.10 μm ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 μm ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance ρ_c is reduced to be less than 1×10^-7 Ω cm, further reduction of the gate overlap capacitance C_ov will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 μm ground rule CMOS at room temperature     

Analysis and design of amplifiers and comparators in CMOS 0.35 μm technology

Design techniques and CAD tools for digital systems are advancing rapidly at decreasing cost, while CMOS analog circuit design is related mostly with the individual experience and background of the designer. Therefore, the design of an analog circuit depends on several factors such as a reliable design methodology, good modeling and technology characterization. Most of this work focuses on the analysis of several analog circuits, including their functionality, using different design methodologies. Initially the determination of two key design parameters (slope factor n and early voltage VA) and the g_m/I_D characteristics were derived from simulations. Then, the analysis and design of three diferent analog circuits are presented. A comparison is made between two design methodology applied to an analog amplifier design. The first one is a conventional approach where transistors are in saturation. The second one is based on the g_m/I_D characteristic, that allows a unified synthesis methodology in all regions of operation of the transistor. The analog modules for comparison and continuous filtering, that find vast applications today, are then analyzed and designed with the parameters and methodology proposed.     

High-speed performance of 0.35 μm CMOS gates fabricated onlow-dose SIMOX substrates with/without an N-well underneath the buriedoxide layer

We present experimental results concerning the propagation delay time of the 0.35 μm CMOS gate chains (inverter, 3NAND, and 3NOR) fabricated on low-dose SIMOX substrates with and without the N-well formed underneath the buried oxide layer in the PMOS region. Using such experimental data as the capacitance voltage characteristics of the buried oxide layer, and the enhanced PMOS transistor drivability due to the negative back bias effect, we clarify the most essential factor of the high-speed performance of the CMOS/SIMOX circuits fabricated on a low-dose SIMOX substrate