A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range

A state variable block diagram method is given for the realization of universal biquadratic transfer functions employing second-generation current-controlled conveyors (CCCIIs). Using minimum number of passive components and properly adjusting the bias currents of CCCIIs, the proposed circuits can realize all the tunable frequency standard filter functions: high-pass, band-pass, low-pass, notch-pass, and all-pass by choosing appropriate input branches without changing the passive elements. These presented circuits are in current-mode and voltage-mode separately. The non-ideality analyses of these configurations are given. Additionally, a high-order low-pass filter derived from the proposed voltage-mode biquadratic filter is introduced. PSPICE simulation results are included to verify the theory.     

A selectable-bandwidth 3.5 mW, 0.03?mm2 self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5?MHz and 65 dB at 10?MHz bandwidth

In this paper we present a dual-mode third-order continuous time $\Upsigma\Updelta$ modulator that combines noise-shaping and pulse-width-modulation (PWM). In our 0.18???m CMOS prototype chip the clock frequency equals 1?GHz, but the PWM carrier is only around 125?MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10?MHz. In the 5?MHz mode the peak SNDR equals 64?dB and the dynamic range 71?dB. In the 10?MHz mode the peak SNDR equals 58?dB and the DR 65?dB. This performance is achieved at an attractively low silicon area of 0.03?mm² and a power consumption of 3.5?mW.     

A 1 GS/s, 31 MHz BW, 76.3 dB dynamic range, 34 mW CT-\Updelta\Upsigma ADC with 1.5 cycle quantizer delay and improved STF

A 1 GS/s continuous-time delta-sigma modulator (CT- $\Updelta\Upsigma$ M) with 31 MHz bandwidth, 76.3 dB dynamic range and 72.5 dB peak-SNDR is reported in a 0.13 μm CMOS technology. The design employs an excess loop delay (ELD) of more than one clock cycle for achieving higher sampling rate. The ELD is compensated using a fast-loop formed around the last integrator by using a sample-and-hold. Further, the effect of this ELD compensation scheme on the signal transfer function (STF) of a feedforward CT- $\Updelta\Upsigma$ architecture has been analyzed and reported. In this work, an improved STF is achieved by using a combination of feed-forward, feed-back and feed-in paths and power consumption is reduced by eliminating the adder opamp. This CT- $\Updelta\Upsigma$ M has a conversion bandwidth of 31 MHz and consumes 34 mW from the 1.2 V power supply. The relevant design trade-offs have been investigated and presented along with simulation results.     

A highly linear and fully-integrated FMCW synthesizer for 60 GHz radar applications with 7 GHz bandwidth

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57–64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (\(\Sigma \Delta\)) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is \(2.04\,\text {mm}^2\), and the total power consumption is 280 mW.     

A 0.4–3.3 GHz low-noise variable gain amplifier with 35 dB tuning range, 4.9 dB NF,and 40 dBm IIP2

This work presents a low-noise variable gain amplifier (LNVGA) in which the IIP2 is very high, and the gain control is applied to improve the system dynamic range, even with the limitations of the CMOS technology. Two stages compose the LNVGA, a low-noise amplifier, that keeps the noise figure (NF) at low values, and a variable voltage attenuator (VVA), that provides the gain variation. We have applied on the VVA the phase cancellation technique, in which the addition of two out-of-phase signals controls the gain. This technique provides a large gain tuning range only if the paths of the two signalsto be added are well balanced; hence, a precise 180 degrees phase difference is required. In this desing we propose an active balun with small imbalance, which creates those signals. The LNVGA was implemented in 130 nm CMOS with a 1.2 V supply. The measurement results show a 35 dB gain tuning range, varying from 10 to ? 25 dB, a 4.9 dB minimum NF, a ? 10 dBm IIP3, and an IIP2 as high as + 40 dBm.     

An in-probe receiver amplifier with 3 dB noise figure and 50 dB dynamic range for medical ultrasound imaging using CMUTs

This paper presents the design and measurements of an in-probe receiver amplifier for ultrasound imaging applications using a capacitive micromachined ultrasonic transducer (CMUT). In such applications, the noise and the dynamic range play very important roles, as the former dictates the minimum input signal level and the latter defines the maximum input signal level that can be applied to a system. This work concentrates on both of these specifications. The amplifier consists of a transimpedance amplifier followed by a voltage gain stage implemented using a current feedback amplifier. It is designed and fabricated using a 180 nm CMOS process. A noise figure of 3 dB is measured for a CMUT model with 10–30 MHz frequency range. The amplifier shows a dynamic range of 50 dB with 0.8 % total harmonic distortion for the full scale input current of 7 µA peak-to-peak.     

A 22?mW 512?MHz CMOS continuous time sigma delta ADC in 1.2?V with 16?MHz signal bandwidth and 70?dB dynamic range

A wide bandwidth continuous time sigma delta analog-to-digital conversion is implemented in 130?nm process. The circuit is targeted for wide bandwidth applications such as video or wireless base-stations. The third-order continuous time sigma delta modulator comprises a third-order RC operational-amplifier-based loop filter and 3-bit internal quantizer operated at 512?MHz clock frequency. To reduce the clock jitter sensitivity, nonreturn-to-zero DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer, and the degradation of modulator stability due to excess loop delay is avoided with this architecture. The sigma delta ADC achieves a 60?dB SNR and a 59.3?dB signal-to-noise-plus-distortion ratio over a 16?MHz signal band at an oversampling ratio of 16. The power consumption of the continuous time sigma delta modulator is 22 mW from the 1.2?V supply.     

A ΣΔ micro accelerometer with 6 µg/√Hz resolution and 130 dB dynamic range

This paper reports the implementation of a low noise, high dynamic-range ΣΔ readout for low cost capacitive Micro-Electro-Mechanical Systems (MEMS) accelerometers. The readout circuit sets the bandwidth of the ΣΔ loop through an extra feedback path, and hence allows the closed loop system to operate with the low noise characteristics similar to a second-order ΣΔ analog-to-digital converter. A thorough noise analysis of the proposed accelerometer shows that the mechanical noise is the most significant source and quantization noise is mostly eliminated. Dynamic range (DR) of the system is improved by minimizing the circuit noise and increasing the full scale range (FSR) by high-voltage pulse feedback. Utilization of these techniques allows the implementation of low cost, low noise, and high DR navigation-grade accelerometers, by eliminating the need for large proof mass, large area MEMS sensors. The proposed system can achieve a minimum of 6.0 µg/√Hz noise floor, 3.2 µg bias instability, and a maximum of 130 dB DR at 1 Hz. A FSR of ±20 g is reported for 6.2 µg/√Hz noise floor. This range can be increased up to ±40 g at the cost of noise performance and DR.     

A low-power,low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S₂₁) and reverse isolation (S₁₂), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S₁₁ better than ?10 dB for frequencies 55.1–59.5 GHz, S₂₂ better than ?10 dB for frequencies 55.1–59.4 GHz, S₁₂ better than ?42.6 dB for frequencies 50–64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4–63 GHz. Additionally, high and flat S₂₁ of 9.9 ± 1.5 dB is achieved for frequencies 50.4–62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50–63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.     

A low-impedance,sub-bandgap 0.6 μm CMOS reference with 0.84% trimless 3-σ accuracy and −30 dB worst-case PSRR up to 50 MHz

Modern mobile applications demand high performance from low supply voltages to reduce power (extend battery life) and survive low breakdown voltages (imposed by sub-micron CMOS technologies), which is why precise low-impedance sub-bandgap references (below 1.2 V) that are independent of process, package stress, supply, load, and temperature are critical. However, improving dc accuracy by trimming requires test time (cost) in production and dynamic-element matching (DEM) introduces switching noise. Additionally, improving ac accuracy by rejecting supply ripple with cascodes increases headroom requirements and shunting coupled noise with series low-impedance buffers introduces temperature-sensitive offsets that degrade dc accuracy. This paper presents a prototyped 0–5 mA, 890 mV, low-impedance, 0.6 μm CMOS reference with a trimless 3-σ unloaded dc accuracy of 0.84% across −40 and 125°C (2.74% when loaded with 0–5 mA and supplied from 1.8 to 3 V) and a worst-case power-supply ripple rejection (PSRR) of −30 dB up to 50 MHz. The design adopts a low-cost, noise-free, self-selecting Survivor scheme to automatically select the best matching pair of devices among a bank of similar pairs during start-up (or power-on reset) and use them for critical functions in the circuit. A compact, low-voltage, charge-pumped cascoding strategy and a bandgap-embedded shunt-feedback loop suppress supply and coupled noise.     

0–30?V common mode range, 120?dB CMRR, and 10?nV/ \sqrt {\text{Hz}} noise floor current shunt monitor IC with an embedded ΣΔ modulated digital interface

Sensing and controlling current flow is a fundamental requirement for many electronic systems, including power management (DC?CDC converters and LDOs), battery chargers, electric vehicles, solenoid positioning, motor control, and power monitoring. Current shunt monitor (CSM) system enables current measurement across an external sense resistor (R _S ) in series to current flow. Proposed CSM system can sense a system (power supply) current from 1 to 500?mA across a typical board Cu-trace resistance of 1??? with less than 10???V input-referred offset, 150?nV/°C offset drift and 0.1% accuracy. Instead of using a costly zero-TC sense resistor (R _S ) that is used in typical CSM systems; proposed method uses existing Cu board trace for sensing. The sense amplifier uses chopper stabilization in the signal chain of the amplifier to suppress input-referred offset down to less than 10???V. Switching current-mode (SI) FIR filtering is used at the instrumentation amplifier output to filter out the chopping ripple at the harmonics of the chopping frequency. A frequency domain Sigma Delta (????FD) ADC enables a digital interface to processor applications. The CSM is fabricated on a 0.7???m CMOS process with three levels of metal with maximum Vds tolerance of 8?V, and operates across a common mode range of 0?C30?V achieving less than 10?nV/ $ \sqrt {\text{Hz}} $ of flicker noise at 100?Hz. By using a semi-digital SI FIR filter, residual chopper ripple is suppressed by more than 7.5?mV_pp from the base line of 8?mV_pp, which is equivalent to 25?dB suppression.     

Formation of ncl-Si in the Amorphous Matrix a-SiOx:H Located near the Anode and on the Cathode,Using a Time-Modulated DC Plasma with the (SiH4–Ar–O2) Gas Phase ( $${{{text{C}}}_{{{{{text{O}}}_{2}}}}}$$ = 21.5 mol %)

Semiconductors - The formation of ncl-Si in the amorphous matrix a-SiOx:H using a time-modulated DC plasma at an elevated oxygen content of $${{C}_{{{{{text{O}}}_{2}}}}}$$ = 21.5 mol % in a gas...