A new compact temperature-compensated CMOS current reference

This paper describes a new circuit integrated on silicon, which generates temperature-independent bias currents. Such a circuit is firstly employed to obtain a current reference with first-order temperature compensation, then it is modified to obtain second-order temperature compensation. The operation principle of the new circuits is described and the relationships between design and technology process parameters are derived. These circuits have been designed by a 0.35 /spl mu/m BiCMOS technology process and the thermal drift of the reference current has been evaluated by computer simulations. They show good thermal performance and in particular, the new second-order temperature-compensated current reference has a mean temperature drift of only 28 ppm//spl deg/C in the temperature range between -30/spl deg/C and 100/spl deg/C.     

A very high performance compact CMOS current mirror

This paper proposes a very high performance current mirror (CM), where output current accurately copies the input current without carrying any offset component. Compact implementation of Garimella et al. CM structure has been combined with super cascode configuration to achieve the proposed very high performance CM. The proposed CM offers extremely high output resistance, very low input resistance and high degree of copying accuracy over a wide operating current range. Small signal analysis is carried out to validate the performance characteristics of the circuit. The proposed CM is simulated by Mentor Graphics Eldospice in TSMC 0.18 µm CMOS, BSIM3 and Level 53 technology, using a single supply voltage of 1.5 V. The circuit is shown to have high current copying accuracy for a range of (0–500 µA) with an error less than 0.0016 % and has no offset current at the output side. The robustness of the proposed CM against the variations in device parameters and temperature changes has been reflected in simulations by carrying Monte Carlo and temperature analysis. The simulation results show that the proposed circuit provides very high output resistance of 55.76 GΩ and a very low input resistance of 0.07 Ω.     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

A compact rail-to-rail output stage for CMOS operational amplifiers

This paper presents a CMOS output stage devised for driving heavy resistive loads. An operational amplifier of this type has been fabricated in a 3 μm double-polysilicon CMOS technology. With a supply voltage of ∓5 V and load of 470 Ω, the amplifier has a ∓4.6-V output swing and features a 60 mA short-circuit output current. Although simple, the proposed configuration enables the output transistors to be driven efficiently     

A compact rail-to-rail CMOS buffer amplifier with very low quiescent current

In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push–pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 μm process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1 nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 μA quiescent current from a 3.3 V power supply.     

A simplified compact model of miniaturized cross-shaped CMOS integrated Hall devices

A simplified compact model for a miniaturized cross-shaped CMOS integrated Hall device is presented.The model has a simple circuit structure,only consisting of a passive network with eight non-linear r...     

Low-voltage wideband compact CMOS variable gain amplifier

A novel low-voltage wideband CMOS variable gain amplifier (VGA) is proposed. Using a 0.13 /spl mu/m CMOS technology, the VGA exhibits a linear-dB controllable gain range of 40 dB with a bandwidth in excess of 130 MHz, while drawing only 50 /spl mu/A from a single 1 V power supply voltage.     

CMOS图像传感器新技术——C^3D

C3D(CMOS Color Captive Device)是新一代半导体成像技术,它不仅提高了像素设计技术,也改进了生产工艺.采用这种技术生产的0.25 μ mCMOS图像传感器能够在不牺牲性能的前提下增加晶体管的数量和占空因数(Fill Factor).除了增加像素设计的选择方案之外,还可实现更为复杂的功能和更低的功耗,并且在速度方面也很有优势.     

A new compact model for external latchup

A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS.     

OTA-based integrable voltage/current-controlled ideal C-multiplier

A capacitance multiplier circuit, using operational transconductance amplifiers, is realised. The circuit provides widerange linear control of the capacitance value with direct voltage or current. This makes the realisation of large-valued grounded capacitors possible in IC fabrication. The linearly tunable capacitor is expected to find attractive applications in voltage/current-controlled filters, oscillators etc.     

A new approach to model CMOS latchup

Based upon the concept of the λ-typeI-Vcharacteristics, CMOS latchup is modeled and latchup criteria are constructed. According to the model and the criteria, conditions which lead to latchup can be expressed in terms of triggering currents, parasitic resistances, and device parameters. Therefore, latchup initiation can be predicted. Both transient simulation results and experimental results coincide with theoretical predictions and calculations. This substantiates the correctness of the proposed model.     

A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies

This paper presents a compact test structure for the characterisation and modelling of leakage currents in sub-micron CMOS technologies, with which all leakage components can be directly extracted automatically and input/output influence is cancelled. The test structure can also be used for measurement of intrinsic I_ddq for defect detection.     

A CMOS fast transient response low-dropout regulator with a compact NMOS output driver

We present a CMOS low-dropout voltage regulator with a high-speed NMOS compact driver suitable for supplying on-chip voltages for the digital core of a SoC. The LDO is part of a power management controller hardblock integrated within a microcontroller. The die area of the circuit implemented in a 90 nm CMOS process is only 0.054 mm². Experimental results show that the developed LDO can supply up to 15 mA and it presents a very fast transient response, with a settling time of approximately 30 ns and a voltage drop of 200 mV when the load current changes from 100 nA to 9 mA.     

New compact CMOS continuous-time low-Voltage analog rank-order filter architecture

A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-/spl mu/m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed.     

Ultrafast compact 32-bit CMOS adders in multiple-output dominologic

A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5× and 1.7× over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9-μm two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25°C with V_DD+5.0 V     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.