A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.     

A 0.6 V and 0.395 pJ/bit nonius TDC for a passive RFID pressure sensor tag

This work presents a nonius time to digital converter (TDC) adapted to a passive RF identification (RFID) pressure sensor tag. The proposed converter exploits the characteristics of time-based sensor interfaces and allows reducing voltage supply and power consumption while maintaining resolution and conversion efficiency. The nonius TDC has been designed and fabricated using the TSMC 90 nm standard CMOS technology. The main blocks of the converter are described and both the resolution adjustment and measurement processes are explained in detail. Measurement results show 10.49 bits of effective resolution for an input time range from 28.19 to 42.93 μs. With a sampling rate of 19 KS/s the converter has a conversion efficiency of 0.395 pJ/bit with a voltage supply of only 0.6 V. This characteristics in the proposed nonius TDC enables an increased reading range of the passive RFID pressure sensor tag.     

A novel mathematical model for coverage in wireless sensor network

1 Introduction With the development of the sensor, wireless communication, and computer science, many researches have been focused on the development of a novel wireless network named wireless Ad-hoc sensor networks. This network can be defined as a network that can be self-organized in Ad-hoc fashion. This includes many sensor nodes and its objective is to sense, collect, and process the information collected by the individual sensor nodes via their cooperation [2]. Because of its high pract…     

A 6 mW 750 MHz anti-aliasing filter for receiver analog front-end

A low power high speed continuous-time filter for receiver application in standard 90 nm CMOS process is presented. A biquad cell based on the open-loop topology is implemented. Besides, a differential voltage buffer with additional gain boost, high linear voltage-to-voltage conversion and low output impedance is introduced. In this work, a fourth-order filter is implemented. Simulation results show the 750 MHz cutoff frequency with less than ?50 dB IM3 for a 300 mVpp input. The power consumption for this filter is 6 mW at a 1.2-V supply.     

A remotely-powered, 20 Mb/s, 5.35 pJ/bit impulse-UWB WSN tag for cm-accurate-localization sensor networks

This paper presents an ultra-low-power, low-voltage sensor node for wireless sensor networks. The node scavenges RF energy out of the environment, resulting in a limited available power budget and causing an unstable supply voltage. Hence, accurate and extensive power management is needed to achieve proper functionality. The fully integrated, autonomous system is described, including the scavenging circuitry with integrated antenna, the power detection and power control circuits, the on-chip clock reference, the UWB transmitter and the digital control circuitry. The wireless sensor node is implemented in \(0.13 \,\upmu \hbox {m}\) CMOS technology. The only external components are a storage capacitor and a UWB transmit antenna. The system consumes only \(113\, \upmu \hbox {W}\) during burst mode, while only 8 nW is consumed during the scavenging operation, enabling an efficiency of 5.35 pJ/bit which is significantly better than current state-of-the-art UWB tags. Due to the use of impulse-radio UWB, also cm-accurate localization of the tag can be achieved.     

A low-power,wide-range variable gain CMOS RF transmitter for 900 MHz wireless communications

This paper presents a low-power, wide-range variable gain RF transmitter for 900 MHz-band wireless communication applications based on a standard 0.18 μm CMOS technology. A very wide-range variable gain and high linearity up-conversion mixer is obtained by using a newly transconductance stage. High linearity at low power dissipation driver amplifier can be obtained by adopting a folded cascode topology with an additional gate-source capacitor. The measured results show conversion gain of 16 dB, dB-linear gain variation of 47 dB with the linearity error less than ±0.5 dB, output P-1 dB of 2 dBm, and OIP3 of 12 dBm while dissipating 4 mA from 1.25 V supply.     

A novel high-isolation RF-SOI switch for 2.4 GHz multi-standard applications

Taking advantage of 1 KΩ·cm high-resistivity substrate and special device structure, a novel stack-by-two Single-pole-double-throw (SPDT) switch is fabricated in 0.18 μm partially depleted silicon-on-insulator technology for power handling capability and linearity improvement, targeting 2.4 GHz multi-standard transceiver application. The measured insertion loss is −1.1 dB at 2.4 GHz. With stacked switching device, the circuit exhibits a high measured input input-referred 1 dB power compression point (IP1 dB) of 21.5 dBm, which has more than 7 dB enhancement compared to previous work. The measured isolation is 43 dB. The switch has a overall occupied die area of 1200 × 560 μm².     

A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 μm 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (DAC) and a fully differential adaptive line driver (LD). In designing the DAC, the switched-current method is used to increase the conversion speed; the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Ω and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, ± 0.874 V, ± 10 mA, 45.8 mW, ?0.80 to +0.62 LSB, and ?0.92 to +0.82 LSB, respectively.     

QSM-IDM – A novel quadrature spatial modulation based on interleaving division multiplexing for multiple antenna system

Quadrature Spatial Modulation (QSM) is a high spectral efficiency Multiple-Input Multiple Output (MIMO) technique used to improve the spectral efficiency of wireless communication systems. The main concept of QSM is to extend the spatial constellation of the conventional Spatial Modulation (SM) in both the in-phase and quadrature components of the data symbol. In this paper, because QSM-based on Interleaving Division Multiplexing (IDM) has not been introduced in the literature as a multiple antenna system, we introduced a novel scheme, called QSM system based on Interleaving Division Multiplexing (QSM-IDM). The antenna sets are also applied to a spreader, before being used to assign an antenna number for information transmission. Analysis and simulations for a flat fading channel show that the proposed QSM-IDM method significantly outperforms the original QSM system with the same data rate, while maintaining a relatively acceptable complexity. The obtained simulation results show that the conducted analysis yields significant improvements for the accuracy of the proposed scheme, with satisfactory complexity.     

A 0.5 V tunable complex filter for Bluetooth and Zigbee using OTAs

A 12th-order low voltage tunable differential complex filter for bluetooth and Zigbee applications is proposed in this paper. The filter is based on improved controllable transconductors operating with the ultra-low supply voltage of 0.5 V. Simulation results using a triple-well 0.13 μm CMOS technology verify the filter operation fulfilling all the requirements for the complex filtering stage in bluetooth or Zigbee receivers. The in-band group delay variation is 0.79 μs for bluetooth and 0.46 μs for Zigbee. The image rejection ratio is greater than 71 dB and the achieved in-band spurious free dynamic range is 42 dB.     

A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments

This work proposes a 12 b 8 kS/s ultra-low-power CMOS algorithmic analog-to-digital converter (ADC) for sensor interface applications such as accelerometers and gyro sensors requiring high-resolution, low-power, and small size simultaneously. The proposed ADC employs switched-bias power reduction and bias sharing circuits to minimize chip area and power dissipation. A signal-insensitive all directionally symmetric layout technique based on a double-poly CMOS process reduces capacitor mismatch in the multiplying D/A converter for 12 b-level high accuracy without additional conventional calibration schemes. Two independently generated currents with the same negative temperature coefficient are subtracted from each other to implement temperature- and supply-insensitive current and voltage references on-chip. The prototype ADC in a 0.35 μm 2P4M CMOS technology demonstrates a measured differential non-linearity and integral non-linearity within 0.15 and 0.56 LSB at 12 b and shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 68 and 77 dB at 8 kS/s, respectively. The ADC with an active die area of 0.70 mm² consumes 16 μW at 8 kS/s and 2.5 V.     

A novel node selection scheme for energy-efficient cooperative spectrum sensing using D–S theory

Wireless Networks - Energy-efficient and reliable detection of available spectrum are fundamental objectives for cooperative spectrum sensing (CSS) in cognitive radio sensor networks (CRSNs). In...     

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

A 16 MHz, 59.2 ppm/°C CMOS DLL-Assisted VCO with Improved Frequency Stability Towards Single Chip Wireless IOT

A 16 MHz, highly stable voltage controlled oscillator (VCO) is reported in this paper. The proposed VCO consists of three cross-coupled RC stages, and is fully compatible with standard CMOS process. A positively biased PN junction with negative temperature coefficient is incorporated in the design to compensate frequency drift. In addition, a delay locked loop (DLL) directly following the VCO is utilized to further improve the output stability caused by temperature variations. The designed circuit was implemented using CMOS 0.18 μm technology, and was validated through experiments. Measurement results show that the DLL-assisted VCO output variation across the 25~120 °C temperature range is less than 0.56 %, corresponding to 59.2 ppm/°C. It also shows that the output standard deviation of the DLL-assisted VCO is only 6.816 KHz, ~ 16.6 % better compared with the same VCO without DLL’s assistance.     

A very compact, 0.4 V DTMOS CCII employed in an audio-frequency filter

This paper presents an ultra low-voltage, ultra low-power, very compact, dynamic threshold voltage MOS transistor (DTMOS)-based CCII circuit. The proposed circuit is capable of operating under ± 0.2 V symmetric supply voltages. The circuit topology is very compact and consists of only four DTMOS transistors and four ordinary NMOS transistors. The total power consumption of the circuit is found as only 214 nW while all transistors are working in the subthreshold region. The current conveyor has 570 kHz 3 dB-bandwidth from X to Y terminal for the voltage gain and has low, 0.2 % following error between these terminals for inputs not exceeding ± 60 mV. TSMC 0.18 µm process technology parameters are used in the design of the proposed CCII block which is then employed in an audio-frequency, second-order, band-pass filter configuration where real speech signals are fed to the input of the filter to further investigate its characteristics. Close agreement is found between theoretical study and simulated responses.