ASIC可测试性设计技术

可测性设计技术对于提高军用ＡＳＩＣ的可靠性具有十分重要的意义。结合可测性设计技术的发展,详细介绍了设计高可靠军用ＡＳＩＣ时常用的ＡｄＨｏｃ和结构化设计两种可测性技术的各种方法,优缺点及使用范围。其中,着重论述了扫描技术和内建自测试技术。     

SOC混合信号测试难题的解决策略

缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法.     

系统芯片的测试技术

简述了片上系统的基本概念,分析了目前片上系统测试技术所面临的问题。对即将成为主流测试方法的内建自测试技术(BIST)进行了详尽地论述,并提出了两种新的BIST综合测试技术。     

面向功耗优化的伪随机测试矢量生成

随着集成电路设计复杂度和工艺复杂度的提高，集成电路的测试面临越来越多的挑战，内建自测试作为一种新的可测性设计方法，能显著提高电路中随机逻辑的可测性，解决一系列测试难题，但它同时也引起了测试功耗问题，本文提出了一种面向功耗优化的伪随机测试向量生成方法，在保证故障覆盖率的条件下，大大降低了测试功耗。     

基于BIST的编译码器IP核测试

介绍了用于IP核测试的内建自测试方法（BIST）和面向测试的IP核设计方法,指出基于IP核的系统芯片（SOC）的测试、验证以及相关性测试具有较大难度,传统的测试和验证方法均难以满足。以编译码器IP核为例,说明了基于BIST的编译码器IP核测试的基本实现原理和具体实现过程,通过加入测试外壳实现了对IP核的访问、隔离和控制,提高了IP核的可测性。     

面向低功耗BIST 的VLSI 可测性设计技术

随着手持设备的兴起和芯片对晶片测试越来越高的要求，内建自测试的功耗问题引起了越来越多人的关注，本文对目前内建自测试的可测性设计技术进行了分析并对低功耗的VLSI可测性设计技术的可行性和不足分别进行了探讨。在文章的最后简单介绍了笔者最近提出的一种低功耗的BIST结构。     

基于电力线通信芯片可测性设计的研究实现

集成电路的快速发展,迫切地需要快速、高效、低成本且具有可重复性的测试方案,这也成为可测性设计的发展方向。此次设计基于一款电力线通信芯片,数字部分采用传统常用的数字模块扫描链测试和存储器内建自测试;同时利用芯片正常的通信信道,引入模拟环路测试和芯片环路内建自测试,即覆盖了所有模拟模块又保证了芯片的基本通信功能,而且最大限度地减少了对芯片整体功能布局的影响。最终使芯片良率在98%以上,达到了大规模生产的要求。此设计可以为当前数模混合通信芯片的测试提供参考。     

混合信号系统中的模拟设计规则

混合信号系统中的模拟设计规则东立摘编在混合信号设计中，要求模拟电路和数字电路在无不利影响的条件下共享同一系统。这虽然像要狐狸和小鸡和平共处一样困难，但目前的许多混合信号系统设计都取得了成功，而且若按照某些规则设计模拟部分，还可获得更好的系统性能。设计...     

数字集成电路故障测试策略和技术的研究进展

IC制造工艺的发展，持续增加着VLSI电路的集成密度，亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上，综述了常规通用测试方法和技术，并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战，本文进行了初步的论述和探讨。     

几种CMOS VLSI的低功耗BIST技术

在分析全扫描内建自测试(BIST)较高测试功耗的基础上,总结出几种CMOS VLSI的低功耗BIST技术方案,包括减少待测电路(CUT)输入端的翻转次数、简化线性反馈移位寄存器(LFSR)结构、部分扫描低功耗BIST方法等.分析结果表明,这些方法不但在保证测试覆盖率的条件下,降低了测试平均功耗和峰值功耗,而且综合应用这几种方法将会使系统功耗指标达到最佳.     

Digital Signature Proposal for Mixed-Signal Circuits

A new Built-In Self-Test structure, based on the information provided by the XY-operation (Lissajous curves) is introduced in this paper. A Digital Signature is obtained which is used to discriminate catastrophic as well as parametric defects. High Fault Coverage is achieved when applying the proposed BIST on an ITC'97 benchmark circuit where 92% of the catastrophic defects and 87.5% of the parametric defects analyzed produced digital signatures clearly distinguishable from the golden signature.     

一种混合信号SoC中模数转换器的内建自测试方案

提出了一种针对混合信号SoC中ADC的动态参数与静态参数测试的内建自测试方案.由于动态参数和静态参数在同一个测试电路中都能够得到测试,因此能够更加全面准确地反映待测器件的性能.通过对存储器和计算资源的合理配置和复用,将两种测试的激励产生和响应分析集成在一起,最大程度地减少了对电路面积的影响.整个设计在FPGA上实现,实验结果证明了其可行性.     

A Unified DFT Approach for BIST and External Test

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.     

Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme

Pseudo-random testing techniques for mixed-signal circuits offer several advantages compared to explicit time-domain and frequency-domain test methods, especially in a BIST structure. To fully exploit these advantages a suitable choice of the pseudo-random input parameters should be done and an investigation on the accuracy of the circuit response samples needed to reduce the risk of misclassification should be carried out. Here these issues have been addressed for a testing scheme based on the estimation of the impulse response of the device under test (DUT) by means of input-output cross-correlation. Moreover, new acceptance criteria for the DUT are suggested which solve some ambiguity problems arising if the classification of the DUT as good or bad is based on a few samples of the cross-correlation function. Examples of application of the proposed techniques to real cases are also shown in order to assess the impact of the measurement system inaccuracies on the reliability of the test.     

Integrated Design and Test of Mixed-Signal Circuits

In this paper, the integration of design and test flows for mixed-signal circuits is discussed. The aim is to decrease test generation and debugging costs and time-to-market for the analogue blocks in mixed-signal circuits. A tool developed in order to automate the data sharing between design and test environments is described and the functionality of this tool is explained. The generation of a test plan consists of the selection of the separate test functions and addition of commands for control signal generation and tester routing. The usage of design data for each of these functions is explained and the tool is evaluated in the design and testing of a mixed-signal demonstrator circuit. Results from this experience are discussed.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

模拟/数字混合信号电路技术发展动态

叙述了国内外模拟和数字混合信号电路发展现状,重点讨论了国内外高性能模拟、射频电路、DSP、A/D转换器和SOC等器件研发和应用的一些情况,指出了这些器件在数模混合信号电路技术发展进程中的作用.     

On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages

A design-for-testability implementation for analogue functional blocks of mixed-signal ASICs is presented. For the analogue blocks direct access via an analogue input pin for the automated test equipment is required. To this end existing OpAmp or OTA stages of the respective analogue blocks are converted into simple clocked comparators. The resulting two-mode comparators are used to observe specific internal nodes of the functional block under test. Depending on the comparator mode, the observed test response evaluation can either be static and/or quasi-dynamic. At least two reference voltages are required each with two different levels determined by a hysteresis. All necessary reference voltages are generated on-chip in the central biasing cell of the ASIC. Due to this Design-for-Testability implementation, an on-chip test evaluation can be performed without the need to bring an analogue signal on- or off-chip. From simulation and measurement results of a feasibility study performed on a general purpose test circuit realised in 0.35 m technology, the applicability was demonstrated. It showed that good fault coverages in the analogue functional blocks can be achieved. Estimations about the biasing programming indicated that this technique is in particular suitable for mixed-signal ASICs larger than 15 mm² with a typical total power consumption of more than 50 mW typical for high voltage applications.     

混合信号电子产品的自动测试技术

电子产品微型化使自动测试成为必然,而边界扫描技术则使自动测试成为可能。文章分析了1149.4和1149.1标准的测试访问端口,以及测试逻辑结构和测试协议的异同,提出了模拟边界扫描单元ABM和数字边界扫描单元DBM的行为模型;在此基础上,详细阐述了两个标准在混合信号电子产品自动测试中的综合应用方法;最后,以典型的混合信号电路D/A转换器为例,对两个标准的综合应用进行了仿真验证。     

高速串行数据接收器专用集成电路的可测性设计

本文为了解决高速串行数据接收器专用集成电路的测试难题．提出了针对该高速工作的集成电路的测试方案．并设计了可行的测试电路．通过添加测试引脚、设计专用测试模式．内建自测试等方法有效的群决了该芯片电路的功能测试和电气性能测试．