集成电路中的电磁兼容（EMC）设计

介绍了集成电路的EMC 问题和EMC 设计方法,重点论述了在集成电路研制过程中,在电路、版图、封装设计 各个阶段EMC 设计的要点。     

Applications of infrared microscopy to IC and MEMS packaging

A high sensitivity, infrared (IR) microscope operating in the wavelength range 800 to 2500 nm has been applied to a variety of packaging related issues. Applications can be divided into three categories. 1) For flip chip devices the advantage of the IR microscope is that most silicon is effectively transparent at wavelengths greater than 1100 nm. This enable defects such as voids, delamination cracks and corrosion to be investigated while the chip is mounted on the substrate. 2) The IR microscope enables thermal images of devices to be obtained with a temperature resolution of approximately 1 K and spatial resolution of 2-3 /spl mu/m. 3) The transparency of silicon to IR radiation has proved particularly valuable for characterising micro-electro-mechanical systems (MEMS) devices such as microphones, at various stages of packaging, e.g., after die bonding and wire bonding.     

A figure of merit for IC packaging

Powering integrated circuits is a compromise between increasing power to increase circuit speed and maintaining high packaging density while satisfying cooling constraints. The optimization of this compromise provides the basis for a packaging figure of merit.     

A comparison of PWB warpage due to simulated infrared and wavesoldering processes

Two types of bare, four layer printed wiring board (PWB) test vehicles were designed and fabricated to replicate simplified versions of typical boards produced by PWB manufacturers. The boards were subjected to simulated infrared and wave soldering reflow processes in a small lab-scale oven integrated with a shadow Moire out-of-plane displacement measurement system. The measured warpages were qualitatively and quantitatively analyzed at selected temperatures during the reflow profiles. The results presented compare and contrast the effects that simulated wave and infrared reflow soldering processes have on the warpage of two different PWB designs     

集成电路的电磁兼容测量标准及需求分析

探讨了集成电路电磁兼容测量标准研究的意义与需求分析,及其对产业发展的影响;介绍了集成电路电磁兼容测量的标准体系.以及标准的发展.     

Reliability challenges in 3D IC packaging technology

At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the packaging. If we assume just a difference of 1 °C across a micro-bump of 10 μm in diameter, the temperature gradient is 1000 °C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what we have known from flip chip technology.     

Mechanism of warpage orientation rotation due to viscoelastic polymer substrates during thermal processing

The warpage orientation, which refers to the direction of maximum and minimum curvatures in a cylindrical warpage, was observed to have changed by flipping from a concave to a convex shape during thermal processing. In this paper, the mechanism of the warpage orientation rotation is demonstrated through analyzing the stress state and curvatures of the specimens using finite element method (FEM) simulations and experiments. It is revealed that the warpage transition temperature, where the curvature changes to other shapes, corresponds to the stationary point of the stress-temperature curve and the curvature change of the minimum direction precedes the curvature change of the maximum direction during the warpage orientation rotation. This precedence results from the stress relaxation of the fiber reinforced polymer (FRP) substrate. Because the curvature of minimum direction flips backward in advance of maximum direction, the cylindrical warpage shape converts to a saddle shape and it induces the rotation of the warpage orientation. The simulation without the viscoelastic properties of the FRP substrate is conducted and used for comparison in order to verify the stress relaxation effect of the warpage orientation rotation phenomenon. In conclusion, it is demonstrated that the viscoelastic properties of the FRP substrate are a critical factor in analyzing the warpage orientation rotation and its behavior.     

精简热模型在集成电路封装中的应用研究

探讨了为一款FBGA封装产品建立DELPHI型热阻网络的新方法。首先利用恒温法为芯片封装建立星型网络,在此基础之上求解支路耦合热阻值,构成DELPHI型热阻网络。经过仿真验证显示,所建立的两种DELPHI型热阻网络模型与详细热模型(DTM)的结温误差均在10%以内,从而具备较好的边界条件独立性。     

Characterisation of IC packaging interfaces and loading effects

In IC packaging, the quality of the interfaces such as that between mold compound and silicon is a critical issue in the reliability testing during the manufacturing process and in-service. Weak interfaces have often gone undetected and may become potentially defective at a later stage. Furthermore, the stress due to mechanical or thermal loading may further deteriorate the interface quality, making the interface unreliable. There is a desire to study the interface quality quantitatively, so potential defects can be evaluated and identified early. In this paper, finite element analysis using multilayer interface model is used to study the reflection coefficient from the interface of varying quality. Different conditioning techniques were used to degrade the interface quality. Characterisation of the interface quality of the MC/Si interface was conducted using longitudinal ultrasonic wave propagation with contact transducers. A combined test that measures the reflection coefficient of the interface under stress load was also conducted to quantify the effect of the load. A nondestructive evaluation methodology is proposed that measures the available strength of the interface by using ultrasonic reflection coefficients, and it shows the correlation between the reflection coefficient and available strength of the interface can be developed and used as a quantitative indicator.     

IC EMC测试认证技术助力国产芯片加速发展

天津市滨海新区军民融合创新研究院物联网感知测试认证中心建有EMC(集成电路、军用设备、汽车电子)、RFID、环境可靠性、感知与探测四大测试认证实验室,均获得CNAS认可,可提供电子设备的系统级、板级、芯片级的EMC、RFID及环境可靠性设计、测试和整改服务。     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

浅析De-flash溶液pH值变化对EMC和导线架间分层的影响

在分析芯片内部分层不良的过程中发现使用N型EMC所生产的产品占据了所有分层不良的绝大多数。对使用N型EMC生产制程中从注胶模压到弯脚成形的每一个步骤完成后均对产品进行超声波探测（SAM）,发现去残胶制程（De-flash）最有可能导致芯片内部分层,而其他制程不会导致分层。EMC是由许多高分子树脂材料及各种添加剂组成,这...     

Characterization of moisture properties of polymers for IC packaging

In this paper we determined the water uptake of a die attach and a molding compound. The two types of polymer which were selected are a die attach filled with silver particles and an epoxy molding compound filled with silica particles. The water absorption is carried out in an adjustable thermal and humidity chamber, SGA-100, at different temperatures and humidity levels. Moisture absorption equilibrium of test data were obtained by experiment. The moisture absorption equilibrium prediction equation was modeled by using the extrapolated experimental data. Diffusion coefficients at different temperature were obtained from the moisture absorption experiments.     

塑封器件芯片与塑封料界面分层的研究

针对一款LQFP塑封器件,利用ANSYS有限软件建立了三维模型,根据断裂参数——J积分,讨论分析了芯片/塑封料界面的三种分层区域模型,得到了分层的主要扩展模型,即凸形分层区域,同时提出了一种分层扩展趋势的新模型,进而对凸形分层模型探讨了温度和裂纹半径对器件分层的影响。仿真数据表明,在极端低温或高温下,器件的分层区域容易扩展;而在一定的应力条件下,裂纹扩展的趋势会受到裂纹半径大小的影响。     

Ultrasonic evaluation of the silicon/copper interfaces in IC packaging

The silicon die and copper lead-frame in integrated circuit (IC) packaging are bonded using a die attach adhesive, and the quality of the adhesive interface is a critical issue in the reliability testing of IC packaging and during the manufacturing process. Common defects such as cracks and delamination can be detected using the C-mode ultrasonic microscopic method with sufficient confidence. However, a weak interface due to weak adhesion and poor cohesion has often gone undetected and may become a potential defect at a later stage. There is a desire to study the interface quality quantitatively, so that any potentially defective area can be evaluated and identified early. This paper describes work in evaluating the quality of the interfaces that typically exist in IC packages by using longitudinal ultrasonic wave propagation with contact transducers. An interface spring model is used to predict the ultrasonic reflection coefficient relationship with varying interfacial spring constants. Experimental results of normal incidence reflection coefficients are obtained from the two-layered specimen bonded with die attach adhesive under varying conditioning process that simulates the degrading of the interface. Good qualitative agreement between the measurement and the prediction is obtained, and shows that the reflection coefficient depends strongly on the interface quality. The study demonstrates that the quantification of the interface quality is possible, using the reflection coefficient as a criterion.     

Investigation of the fluid/structure interaction phenomenon in IC packaging

In the present study, experiment and simulation studies were conducted on the fluid/structure interaction (FSI) analysis of integrated circuit (IC) packaging. The visualisation of FSI phenomenon in the actual package is difficult due to limitations of package size, available equipment, and the high cost of the experimental setup. However, the experimental data are necessary to validate the simulation results in the FSI analysis of IC packaging. Scaled-up package size was fabricated to emulate the encapsulation of IC packaging and to study the effects of FSI phenomenon in the moulded package. The interaction between the fluid and the structure was observed. The deformation of the imitated chip was studied experimentally. The air-trap mechanism that occurred during the experiment is also presented in this paper. Simulation technique was utilised to validate the experimental result and to describe the physics of FSI. The predicted flow front was validated well by the experiment. Hence, the virtual modelling technique was proven to be excellent in handling this problem. The study also extends FSI modelling in actual-size packaging.     

Simulations and experiments of three-dimensional paddle shift for IC packaging

Paddle shift is one of the most serious defects which may arise during the IC encapsulation of leadframe-type packages. The term “paddle shift” means the deflection of the leadframe-pad and die as a result of the pressure difference between the top and bottom mold cavities. In extreme cases, paddle shift could lead to a substantial reduction in the reliability of package.This paper employed a computational approach to predict the paddle shift quantity during the IC packaging process. The approach was based on precise finite element (FE) models and flow-structure decoupled analyses. Two kinds of FE models were needed for the decoupled analyses, namely a 3D FE model for the mold filling analysis (i.e. fluid-flow mesh) and a 3D FE model for the structural analysis (i.e. paddle mesh). The aim of the mold filling analysis was to identify the pressure distribution acting on the paddle structure during the encapsulation process, while the objective of the structural analysis was to determine the amount of paddle shift which was caused by pressure distribution.To investigate the relationship between the package geometry and the amount of paddle shift, the present simulations considered six TQFP (Thin quad flat package) models with different geometrical parameters. The simulation results for the paddle shift were compared with the experimental results to demonstrate the accuracy of the proposed numerical approach. It was found that a good agreement exists between the two sets of results.     

EMC材料特性对MEMS加速度计封装可靠性的影响

采用有限元法分析了EMC(环氧模塑封材料)材料特性对MEMS(微电子机械系统)加速度计封装可靠性的影响.使用有限元软件ANSYS分别模拟了加速度计的输出电压、悬臂梁的挠度以及加速度计芯片的等效应力在温度循环载荷下的变化情况.结果发现,EMC的材料模式不同,MEMS加速度计的性能有明显差异.在使用EMC温度相关弹性模式和...     

基于BP神经网络的模塑封材料疲劳寿命预测

根据模塑封材料(EMC)疲劳实验,针对BP神经网络[反向传播神经网络(BPNN)]拟合误差与预测误差关系不稳定的应用问题,结合主成分分析法,"主动"改善网络结构,建立了基于BP神经网络的EMC材料疲劳寿命预测模型,进行了分析,并与一般的BP神经网络模型作了比较。结果表明,该方法得到的BP神经网络经过训练后能稳定表征EMC材料的各种参数与疲劳寿命间的内在关系。当网络拓扑结构为2-4-1时,预测结果稳定,预测误差平方和(SSE)为0.5623～0.0271,拟合误差(MSE)为0.0906～0.0278,具有实用性。     

移动通讯类HDI板的弯翘研究

由于近几年移动通讯类产品向轻、薄的迅猛发展,而承载部件主板的重量、厚度、体积等起到决定性的作用,故适合此类产品的新型材料薄布基材应用而生,本文主要阐述PCB制造端对板弯翘的预防、改善及矫正方法。