双极型微波功率晶体管热失效原因分析

阐述了双极型微波功率晶体管的主要失效模式及失效机理,重点分析了热应力导致的失效,介绍了两个典型的失效分析案例．并提出相应的筛选措施。     

微波GaAs场效应晶体管静电失效的机理及提高其抗静电的…

本文对微波小功率ＧａＡｓ场效应晶体管的静电失效机理进行了分析。文中对两种静电失效模式（电压型强电场失效和功率型大电流失效）分别进行了分析和阐述。针对ＧａＡｓ场效应晶体管的失效机理提出了改进措施。     

塑封双极型功率晶体管的失效与案例分析

由于其自身的结构与封装形式,塑封双极型功率管存在很多可靠性问题.介绍了塑封双极型功率晶体管可靠性问题及失效机理,包括封装缺陷、粘结失效以及由于温度变化而引起的热应力失效和由于吸入潮气而导致的腐蚀失效.通过剖析一晶体管的失效机理,给出了对此类晶体管失效分析的方法和思路.讨论了晶体管存在异物、芯片粘结失效和热应力失效等失效模式.     

双极型静电感应晶体管特性转变机理分析

本文对双极型静电感应晶体管（ＢＳＩＴ）的工作机理进行了二维分析，给出了明确的ＢＳＩＴ从单极作用机制到双转变过程的物理图象。得到了作用机制转变时的栅压、势分布以及载流子和电场分布等的数值计算结果。     

InGaP异质结双极晶体管ESD特性研究

研究了高速射频集成电路(RF IC)中InGaP异质结双极晶体管(HBT)器件的特性.测试了单指发射极和双指发射极两种结构器件的大信号DC I-V特性及抗人体模型(HBM)静电放电(ESD)能力.结果表明,双指发射极器件比单指器件能传导更高密度的电流,并能抵抗高能量的ESD;两种器件的击穿特性相似.这些结果可以用来指导RF IC ESD保护电路的设计.     

Si/a-Si:H异质结微波双极型晶体管实验研究

本文首次报道采用重掺杂的氢化非晶硅(n~+a-Si∶H)作发射极的硅微波双极型晶体管的制备和特性.该器件内基区方块电阻2kΩ/□,基区宽度0.1μm,共发射极最大电流增益21(V_(cB)=6V,I_c=15mA),发射极Gummel数G_B值已达1.4×10~(14)Scm~(-4).由S参数测得电流增益截止频率f_s=5.5GHz,最大振荡频率f_(max)=7.5GHz.在迄今有关Si/a-Si HBT的报道中,这是首次报道可工作于微波领域里的非晶硅发射极异质结晶体管.     

多模计数器静电放电损伤的失效分析

静电放电(ESD)损伤会降低半导体器件和集成电路的可靠性并导致其性能退化.针对一款国产2-32型多模计数器的失效现象,通过分析该计数器的电路结构,利用X射线成像、显微红外热成像、光束感生电阻变化以及钝化层、金属化层去除等技术对计数器进行了失效分析,将失效点准确定位至输出端口逻辑单元电路的2只晶体管上.分析结果表明,多模计数器的ESD损伤使输出端口驱动晶体管以及为负载晶体管提供栅偏置的前级电路晶体管同时受损,导致计数器端口高、低电平输出均失效而丧失计数功能.对相关的失效机理展开了讨论,同时提出了在电路研制和使用过程中的ESD防护措施.     

微波功率晶体管的热失效分析

微波功率晶体管是微波功率放大器中的核心器件,其热性能在很大程度上决定于封装管芯的管壳.针对某型号的微波功率晶体管在进行生产筛选的功率老化试验时出现的热失效问题进行分析与讨论,最终确定器件管壳内用于烧结管芯的氧化铍(BeO)上的多层金属化层存在质量缺陷,使管芯到BeO的热阻增大,因此出现了老化时部分器件失效现象.提出了预防措施,既可避免损失,也能保证微波功率晶体管在使用中的可靠性.     

静电放电模型及其失效特征

本文介绍了人体模型、机器模型和带电器件模型等三种静电放电模型及其模拟测试方法,重点对这三种静电放电模型的失效特征进行了对比分析.对这些失效特征的深入了解,有助于工程师在失效分析时能够判断出静电放电的类型,从而更有效地帮助调查静电放电的根源.     

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

Electrostatic discharge(ESD) phenomena involve both electrical and thermal effects,and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability.Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors(BJTs) under ESD conditions has been investigated theoretically and experimentally.100 samples have been tested for multiple pulses until a failure occurred.Meanwhile,the distributions of electric field,current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici.There is a good agreement between the simulated results and failure analysis.In the case of a thermal couple,the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects.The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure.When the ESD level increased to 1.3 kV,the collector-base junction has been burnt out first.The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic.In addition,fatigue phenomena are observed during ESD testing,with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.     

静电放电模拟器电路建模分析

从实际的静电放电模拟器结构出发,根据接触放电时静电放电电流的主要特征,考虑到静电模拟器本身、连接线及回路电缆与地平面间产生的分布参数的影响,建立了一个新的静电放电模拟器等效电路模型,并用PSPICE软件对等效电路进行模拟分析,得到了与实测波形基本一致的电流波形.利用该模型讨论了各分布参数对放电电流的影响.结果表明:模拟器体电阻与地间的电感对电流波形影响不大,因此可以忽略,但其与地之间的分布电容对电流波形的低频段有重要影响;连接线分布参数对电流波形的第一峰值及波形光滑度都有影响;回路电缆分布参数主要影响了电流波形中第二个波峰峰值及其位置.     

晶体管加速寿命研究

Choosing small and medium power switching transistors of the NPN type in a 3DK set as the study object,the test of accelerating life is conducted in constant temperature and humidity,and then the data are statistically analyzed with software developed by ourselves.According to degradations of such sensitive parameters as the reverse leakage current of transistors,the lifetime order of transistors is about more than 10~4 at 100℃and 100% relative humidity(RH) conditions.By corrosion fracture of transistor outer leads and other failure modes,with the failure truncated testing,the average lifetime rank of transistors in different distributions is extrapolated about 10~3. Failure mechanism analyses of degradation of electrical parameters,outer lead fracture and other reasons that affect transistor lifetime are conducted.The findings show that the impact of external stress of outer leads on transistor reliability is more serious than that of parameter degradation.     

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×10³ A/cm² at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.     

对GERBER线段失效引起铣带错误的分析与应对

对于PCB制造厂商而言,Genesis作为一个CAM处理软件已经在普遍的使用,通过其自动化功能可以减少CAM前处理偶尔会接到一线员工反馈铣带失效的问题。本文将从铣带失效的原因分析、应对措施上进行论述。     

微波组件设计中的腔体效应

微波有源模块因为腔体的原因造成自激和传输参数的恶化一直是微波电路设计的难点之一.目前没有完整的理论来支持微波有源电路模块的腔体设计.本文从理论上分析了以微带线作为主要微波传输载体的微波组件的腔体效应,借助电磁场仿真工具HFSS对装有微带电路的微波组件进行了仿真.根据仿真结果设计X波段微波组件,并对S参数进行了测试,测试...     

sol-gel法制备微波介质陶瓷材料

以Ｚｒ（ＮＯ３）４·５Ｈ２Ｏ、Ｔｉ（ＯＣ４Ｈ９）４、ＳｎＣｌ４·５Ｈ２Ｏ为原料,用溶胶－凝胶法制备了Ｚｒ－Ｔｉ－Ｓｎ系微波介质超微粉料。实验表明：温度、湿度、溶液浓度、ｐＨ值等是影响形成溶胶、凝胶的主要因素。采用合适的工艺参数能制备出高Ｑ值的微波介质陶瓷微粉。     

CMOS反相器在高功率微波下闩锁效应的温度影响

The temperature dependence of the latch-up effects in a CMOS inverter based on 0.5 μm technology caused by high power microwave （HPM） is studied. The malfunction and power supply current characteristics are revealed and adopted as the latch-up criteria. The thermal effect is shown and analyzed in detail. CMOS in- verters operating at high ambient temperature are confirmed to be more susceptible to HPM, which is verified by experimental results from previous literature. Besides the dependence of the latch-up triggering power P on the ambient temperature T follows the power-law equation P = ATβ. Meanwhile, the ever reported latch-up delay time characteristic is interpreted to be affected by the temperature distribution. In addition, it is found that the power threshold increases with the decrease in pulse width but the degree of change with a certain pulse width is constant at different ambient temperatures. Also, the energy absorbed to cause latch-up at a certain temperature is basically sustained at a constant value.     

硅脉冲微波功率器件增益退化机理研究

介绍了硅双极型微波功率晶体管的发展历史和应用现状.针对硅脉冲微波功率器件增益退化的失效模式,通过对硅脉冲微波功率器件直流参数的统计分析,初步得出了其失效机理.     

GaAs场效应晶体管不同极性ESD损伤机理

对GaAs场效应晶体管(FET)进行3个正向和3个负向脉冲(3“+”3“-”)、3个负脉冲(3“-”)、3个正脉冲(3“+”)3种极性静电放电(ESD)实验,不同极性ESD实验下器件的失效阈值不同.以栅源端对为例对实验结果进行分析,在3“+”3“-”和3“-”极性下,器件失效模式为栅源短路,在3“+”极性下器件电参数退化.运用热模型对ESD正负脉冲电压产生的温升进行了计算,器件的损伤机理为,在正向脉冲下为栅金属纵向电迁移导致肖特基势垒退化;在ESD负向脉冲下为高电场引起栅源端对击穿.