Extraction of density-of-states in amorphous InGaZnO thin-film transistors from temperature stress studies

The instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with different active layer thicknesses under temperature stress has been investigated through using the density-of-states (DOS). Interestingly, the a-IGZO TFT with 22 nm active layer thickness showed a better stability than the others, which was observed from the decrease of interfacial and semiconductor bulk trap densities. The DOS was calculated based on the experimentally-obtained activation energy (E_A), which can explain the experimental observations. We developed the high-performance Al₂O₃ TFT with 22 nm IGZO channel layer (a high mobility of 7.4 cm²/V, a small threshold voltage of 2.8 V, a high I_on/I_off 1.8 × 10⁷, and a small SS of 0.16 V/dec), which can be used as driving devices in the next-generation flat panel displays.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Effect of Ge doping on the electrical properties of amorphous Zn–Sn–O thin films

We report the effect of germanium doping on the active layer of amorphous Zinc–Tin-Oxide (a-ZTO) thin film transistor (TFT). Amorphous thin film samples were prepared by RF magnetron sputtering using single targets composed of Zn₂Ge_0.05Sn_0.95O₄ and Zn₂SnO₄ with variable oxygen contents in the sputtering gases. In comparison with undoped, Ge-doped a-ZTO films exhibited five order of magnitude lower carrier density with a significantly higher Hall-mobility, which might be due to suppressed oxygen vacancies in the a-ZTO lattice since the Ge substituent for the Sn site has relatively higher oxygen affinity. Thus, the bulk and interface trap densities of Ge-doped a-ZTO film were decreased one order of magnitude to 7.047 × 10¹⁸ eV⁻¹cm⁻³ and 3.52 × 10¹¹ eV⁻¹cm⁻², respectively. A bottom-gate TFT with the Ge-doped a-ZTO active layer showed considerably improved performance with a reduced SS, positively shifted V_th, and two orders of magnitude increased I_on/I_off ratio, attributable to the doped Ge ions.     

Investigation of the electrical properties and stability of HfInZnO thin-film transistors

In this study, amorphous HfInZnO (a-HIZO) thin films and related thin-film transistors (TFTs) were fabricated using the RF-sputtering method. The effects of the sputtering power (50–200 W) on the structural, surface, electrical, and optical properties of the a-HIZO films and the performance and NBIS stability of the a-HIZO TFTs were investigated. The films’ N_e increased and resistivity decreased as the sputtering power increased. The 100 W deposited a-HIZO film exhibited good optical and electrical properties compared with other sputtering powers. Optimization of the 100 W deposited a-HIZO TFT demonstrated good device performance, including a desirable μ_FE of 19.5 cm²/Vs, low SS of 0.32 V/decade, low V_th of 0.8 V, and high I_on/I_off of 10⁷, respectively. The 100 W deposited a-HIZO TFT with Al₂O₃ PVL also exhibited the best stability, with small V_th shifts of -2.2 V during NBIS testing. These high-performance a-HIZO thin films and TFTs with Al₂O₃ PVL have practical applications in thin-film electronics.     

Improvement of electrical characteristics of InGaZnO thin film transistors by using HMDSO/O2 plasma deposited SiOCH buffer layer

In this work, we present the performance improved InGaZnO thin film transistors by inserting low temperature processed 10 nm thick SiOCH buffer layers between SiN_x insulator and InGaZnO channel layer. The influences of oxygen flow rate during the deposition of SiOCH buffer layer have been intensively investigated. Basing on the analysis of hall effect measurement and Fourier transform infrared spectrum, the SiOCH buffer layer can effectively increase the carrier concentration of the channel layer by the hydrogen doping due to re-sputtering and diffusion effect. The InGaZnO thin film transistor with buffer layer exhibits an enhanced performance with mobility of 13.09 cm²/vs, threshold voltage of −0.55 V and I_on/I_off over 10⁶.     

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm² V⁻¹ s⁻¹) and low sub-threshold swing (0.57–0.69 V decade⁻¹) compare of the ZnO single layer TFT (μ_FE = 5.38 cm² V⁻¹ s⁻¹; S.S. = 0.86 V decade⁻¹). Moreover, in the results of the positive bias stress, the ΔV_on shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔV_on = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

Gadolinium scandate as an alternative gate dielectric in field effect transistors on conventional and strained silicon

Long channel n-type metal oxide semiconductor field effect transistors on thin conventional and strained silicon on insulator substrates have been prepared by integrating gadolinium scandate as high-κ gate dielectric in a gate last process. The GdScO₃ films were deposited by electron beam evaporation and subsequently annealed in oxygen atmosphere. Electrical characterization of readily processed devices reveals well behaved output and transfer characteristics with high I _on/I _off ratios of 10⁶–10⁸, and steep inverse subthreshold slopes down to 66 mV/dec. Carrier mobilities of 155 cm²/Vs for the conventional and 366 cm²/Vs for the strained silicon substrates were determined.     

Organic/inorganic interfaced field-effect transistor properties with a novel organic semiconducting material

A novel 1,3,4-oxadiazole-substituted benzo[b]triphenylene was synthesized by three-step synthetic procedure and OFET device design was successfully designed after theoretical calculations made using Gaussian software. For investigating the field-effect properties of designed organic electronic device, a SiO₂ (300 nm) was thermally grown on p-Si wafer at 1000 °C as a dielectric layer and gate, source and drain contacts have been deposited using Au metal with physical vapour deposition. 1,3,4-Oxadiazole-substituted benzo[b]triphenylene was spin coated on the source and drain electrodes of our device, forming organic/inorganic interfaced field-effect transistors. Surface morphology and thin film properties were investigated using AFM. All electrical measurements were done in air ambient. The device showed a typical p-type channel behaviour with increasing negative gate bias voltage values. Our results have surprisingly shown that the saturation regime of this device has high mobility (μ_FET), excellent on/off ratio (I_on/I_off), high transconductance (g_m) and a small threshold voltage (V_Th). The values of μ_FET, I_on/I_off, g_m and V_Th were found as 5.02 cm²/Vs, 0.7 × 10³, 5.64 μS/mm and 1.37 V, respectively. These values show that our novel organic material could be a potential candidate for organic electronic device applications in the future.     

Low voltage organic field effect transistors with a poly(hexylthiophene)–ZnO nanoparticles composite as channel material

We report on solution processable organic field effect transistors prepared using a poly(3‐hexylthiophene)–ZnO nanoparticles composite as channel semiconductor material and cross‐linked polyvinyl alcohol as gate insulator. Our transistors show a field effect mobility of 0.35 ± 0.06 cm²/V s, threshold voltage of –1.30 ± 0.11 V, and I_on/I_off ratio of (1.0 ± 0.1) × 10³. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

Utilization of surface plasmon resonance of Au/Pt nanoparticles for highly photosensitive ZnO nanorods network based plasmon field effect transistor

Hydrothermally processed highly photosensitive ZnO nanorods based plasmon field effect transistors (PFETs) have been demonstrated utilizing the surface plasmon resonance coupling of Au and Pt nanoparticles at Au/Pt and ZnO interface. A significantly enhanced photocurrent was observed due to the plasmonic effect of the metal nanoparticles (NPs). The Pt coated PFETs showed I_on/I_off ratio more than 3 × 10⁴ under the dark condition, with field-effect mobility of 26 cm² V⁻¹ s⁻¹ and threshold voltage of −2.7 V. Moreover, under the illumination of UV light (λ = 350 nm) the PFET revealed photocurrent gain of 10⁵ under off-state (−5 V) of operation. Additionally, the electrical performance of PFETs was investigated in detail on the basis of charge transfer at metal/ZnO interface. The ZnO nanorods growth temperature was preserved at 110 °C which allowed a low temperature, economical and simple method to develop highly photosensitive ZnO nanorods network based PFETs for large scale production.     

A short review on: Optimization techniques of ZnO based thin film transistors

There has been a significant global interest in the thin film transistor (TFT) due to its potential use in flat panel display. A great deal of interest in zinc oxide (ZnO) based TFT has been developed owing to its promising electronic and optoelectronic properties. The performance of a TFT is mainly measured by calculating the turn-on voltage, drain current on-to-off ratio (I_on/I_off) and channel mobility that depends on many factors like crystallanity of the active layer, quality of the insulator, and the quality of the interface between the different layers (semiconductor, insulator, and metallic contacts). All these factors further depend upon the growth and processing condition of different layers. This paper presents a short review that includes the factors affecting the performance of ZnO-based TFT and the methods to optimize them. The related work of reputed research groups are summarized and discussed systematically in the paper.     

Characterization of magnesium oxide gate insulators grown using RF sputtering for ZnO thin-film transistors

A ZnO thin-film transistor (TFT) with an MgO insulator was fabricated on a silicon (100) substrate using a radiofrequency magnetron sputtering system. The MgO insulator was deposited using the same deposition system; the total pressure during the deposition process was maintained at 5 mTorr, and the oxygen percentage of O₂/(Ar + O₂) was set at 30%, 50%, or 70%. The process temperature was maintained at below 300 °C. The dielectric constant of the MgO thin layer was approximately 11.35 with an oxygen percentage of 70%. This ZnO TFT displayed enhanced transistor properties, with a field-effect mobility of 0.0235 cm² V⁻¹ s⁻¹, an I_ON/I_OFF ratio of ∼10⁵, and an SS value of 1.18 V decade⁻¹; these properties were superior to those measured for the MgO insulators synthesized using oxygen percentages of 30% and 50%.     

Free-standing tetracene single crystal field effect transistor

We have fabricated and studied field effect transistors (FETs) on the optically transparent free-standing organic single crystals of tetracene. These FETs exhibit effective hole channel mobility μ_eff up to 0.15 cm²/Vs and on-off ratios up to 2×10⁷. Using measured values of μ_eff, thermal activation energy, and a simple model, we deduce an intrinsic free carrier mobility in the range of tens of cm²/Vs, similar to that found in pentacene crystals. These values should be considered only as a rough indication of achievable mobilities in samples much purer than those presently studied. The obtained results show the possibility of FET behavior in transparent crystals with low intrinsic carrier density.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Thin film transistors based on TiO2 fabricated by using radio-frequency magnetron sputtering

This study demonstrates that nanocrystalline TiO₂ thin films were deposited on ITO/glass substrate by radio-frequency magnetron sputtering. Field-emission scanning electron microscope (FE-SEM) and atomic force microscopic (AFM) images showed the morphology of TiO₂ channel layer with grain size and root-mean-square (RMS) roughness of 15 and 5.39 nm, respectively. TiO₂ thin-film transistors (TFTs) with sputter-SiO₂ gate dielectric layer were also fabricated. It was found that the devices exhibited enhancement mode characteristics with the threshold voltage of 7.5 V. With 8-μm gate length, it was also found that the I_on/off ratio and off-state current were around 1.45×10² and 10 nA, respectively.     

Thermally evaporated CdS/CdTe thin film solar cells: Optimization of CdCl2 evaporation treatment on absorber layer

CdCl₂ treatment is crucial in the fabrication of highly efficient CdS/CdTe thin-film solar cells. This study reports a comprehensive analysis of thermal evaporated CdS/CdTe thin-film solar cells when the CdTe absorber layer is CdCl₂ annealed at temperatures from 340 to 440 °C. Samples were characterized for structural, optical, morphological and electrical properties. The films annealed at 400 °C showed better crystallinity with a cubic zinc blende structure having large grains. Higher refractive index, optical conductivity, and absorption coefficient were recorded for the CdTe films annealed at 400 °C with CdCl₂. Optimum photoactive properties for CdS/CdTe thin-film solar cells were also obtained when samples were annealed at 400 °C for 20 min with CdCl₂, and the best device exhibited V_OC of 668.4 mV, J_SC of 13.6 mA cm⁻², FF of 53.9% and an efficiency of 4.9%.