Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Impact of work function variation for enhanced electrostatic control with suppressed ambipolar behavior for dual gate L-TFET

The favorable electrostatic potential and tunneling underneath the overall gate region, which prevents legitimate source to drain tunneling, controllability over the gate is assisted in vertical TFET configurations. An L-TFET (L-shaped Tunneling Field-Effect Transistor) has a larger tunneling length than a veritable TFET. As a consequence, the current in the on-state (I_on) has gotten better. The increased ambipolar current and low I_on/I_off ratio of L-TFET will need to be tuned for low-power and high-frequency functionality. On the other hand, significantly worse switching performance and distortions may lead to a weak robust device. By establishing a high-k gate oxide-based drain underlap region with dual gate, this study is dedicated to ameliorating the I_on/I_off by subverting ambipolar behavior. To investigate the impact of height of second gate (H_gate2) and work-function of this (WF_gate2), EBD (Energy Band Diagram), electric field distribution in X and Y direction, potential and recombination rate are examined under various conditions. Which leads to enhanced DC/RF and linearity performance. Along with this, Current-Voltage characteristics, DC/RF, and linearity performance Figure of Merits (FOMs) also investigated the assessment of variation of H_gate2 and WF_gate2, and it is optimized for the better suppression of I_ambi (ambipolar current) with a steep slope in transfer characteristics. In addition to that, Current-voltage statistics (I_ds − V_gs), DC/RF, and linearity efficiency FOMs were being used to assess the influence of changing the H_gate2 and WF_gate2, which was modulated for greater I_ambi suppression (ambipolar current) with improved SS and V_th for the proposed device.     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

A novel 4H–SiC MESFET with modified channel depletion region for high power and high frequency applications

In this paper, a novel 4H–SiC metal semiconductor field effect transistor (MESFET) with modified depletion region is introduced. The key idea in this work is modifying the depletion region in the channel for improving the electrical performances. The proposed structure consists of upper and lower gates. Also, the lower gate is divided into a number (N) of smaller step-shaped sections. Therefore, we have called the proposed structure multiple-recessed 4H–SiC MESFET (MR-MESFET). DC and RF characteristics of the MR-MESFET structure with various lower gate segments are analyzed by 2D numerical simulation. The simulated results show that as the number of the lower gate sections increases, the channel depletion region is modified and the drain current (I_D) enhances. Also, by increasing the number of the lower gate sections, the breakdown voltage (V_BR) enhances, too. Improvement of the I_D and V_BR leads to a further increase in the output power density of the device. Also, cut-off frequency (f_T), maximum oscillation frequency (f_max), and maximum available gain (MAG) improvements are achieved for the MR-MESFET structure with further number of the lower gate sections. The results show that the MR-MESFET structure with higher number of the lower gate segments has superior electrical characteristics and performances in comparison with the MR-MESFET structure with fewer number of the lower gate sections.     

3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method

In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I _on /I _off , less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Physical simulations and experimental results of 4H—SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H--SiC metal semiconductor field effect transistors (MESFETs) on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H--SiC MESFETs with 100~μm gate periphery. At 30~V drain voltage, the maximum current density is 440~mA/mm and the maximum transconductance is 33~mS/mm. For the continuous wave (CW) at a frequency of 2~GHz, the maximum output power density is measured to be 6.6~W/mm, with a gain of 12~dB and power-added efficiency of 33.7％. The cut-off frequency (f_T) and the maximum frequency (f_max) are 9~GHz and 24.9~GHz respectively. The simulation results of f_T and f_max are 11.4~GHz and 38.6~GHz respectively.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Organic/inorganic interfaced field-effect transistor properties with a novel organic semiconducting material

A novel 1,3,4-oxadiazole-substituted benzo[b]triphenylene was synthesized by three-step synthetic procedure and OFET device design was successfully designed after theoretical calculations made using Gaussian software. For investigating the field-effect properties of designed organic electronic device, a SiO₂ (300 nm) was thermally grown on p-Si wafer at 1000 °C as a dielectric layer and gate, source and drain contacts have been deposited using Au metal with physical vapour deposition. 1,3,4-Oxadiazole-substituted benzo[b]triphenylene was spin coated on the source and drain electrodes of our device, forming organic/inorganic interfaced field-effect transistors. Surface morphology and thin film properties were investigated using AFM. All electrical measurements were done in air ambient. The device showed a typical p-type channel behaviour with increasing negative gate bias voltage values. Our results have surprisingly shown that the saturation regime of this device has high mobility (μ_FET), excellent on/off ratio (I_on/I_off), high transconductance (g_m) and a small threshold voltage (V_Th). The values of μ_FET, I_on/I_off, g_m and V_Th were found as 5.02 cm²/Vs, 0.7 × 10³, 5.64 μS/mm and 1.37 V, respectively. These values show that our novel organic material could be a potential candidate for organic electronic device applications in the future.     

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on-off current ratio (I_on/I_off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.     

C-V characterization of Schottky- and MIS-gate SiGe/Si HEMT structures

Electrical properties of Schottky- and metal-insulator-semiconductor (MIS)-gate SiGe/Si high electron mobility transistors (HEMTs) were investigated with capacitance-voltage (C-V) measurements. The MIS-gate HEMT structure was fabricated using a SiN gate insulator formed by catalytic chemical vapor deposition (Cat-CVD). The Cat-CVD SiN thin film (5 nm) was found to be an effective gate insulator with good gate controllability and dielectric properties. We previously investigated device characteristics of sub-100-nm-gate-length Schottky- and MIS-gate HEMTs, and reported that the MIS-gate device had larger maximum drain current density and transconductance (g_m) than the Schottky-gate device. The radio frequency (RF) measurement of the MIS-gate device, however, showed a relatively lower current gain cutoff frequency f_T compared with that of the Schottky-gate device. In this study, C-V characterization of the MIS-gate HEMT structure demonstrated that two electron transport channels existed, one at the SiGe/Si buried channel and the other at the SiN/Si surface channel.     

A novel double-recessed 4H-SiC MESFET with partly undoped space region

In this paper, a novel double-recessed 4H-SiC metal semiconductor field effect transistor (MESFET) with partly undoped space region (DRUS-MESFET) is introduced. The key idea in this work is to improve the DC and RF characteristics of the device by introducing an undoped space region. Using two-dimensional and two-carrier device simulation, we demonstrate that breakdown voltage (V_BR) increases from 109 V in conventional double recessed MESFET (DR-MESFET) structure to 144.5 V in the DRUS-MESFET structure due to the modified channel electric field distribution of the proposed structure. The maximum output power density of the DRUS-MESFET structure is about 25.4% larger than that of the DR-MESFET structure. Furthermore, lower gate-drain capacitance (C_GD), higher cut-off frequency (f_T), larger maximum available gain (MAG), and higher maximum oscillation frequency (f_max) are achieved for the DRUS-MESFET structure. The results show that the f_max and f_T of the proposed structure improve 95.6% and 13.07% respectively, compared with that of the DR-MESFET structure. Also, the MAG of the DRUS-MESET is 4.5 dB higher than that of the DR-MESFET structure at 40 GHz. The results show that the DRUS-MESFET structure has superior electrical characteristics and performances in comparison with the DR-MESFET structure.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

A comparative study of SELBOX-JLT and SOI-JLT

Analysis of thermal and electrical characteristics of the proposed device, selective buried oxide junctionless transistor (SELBOX-JLT) along with its analog performance, is compared with silicon on insulator junctionless transistor (SOI-JLT). The proposed device shows better thermal efficiency. The maximum device temperature of SELBOX-JLT is 311 K, much less than that of SOI-JLT (445 K). The proposed device has almost no effect of self-heating on output characteristics. SELBOX-JLT exhibits better I _ON/I _OFF ratio, subthreshold slope, and drain-induced barrier lowering as compared to SOI-JLT for the same channel length. The analog performance parameters as transconductance (G _m ), transconductance/drain current ratio (G _m /I _D), drain conductance (G _D), output resistance (R ₀), intrinsic gain (G _m R ₀), and unity-gain frequency (f _T ) of the proposed device are found to be better than SOI-JLT.     

Effect of Temperature Variation on the Characteristics of Microwave Power AlGaN/GaN MODFET

The prime motivation for developing the proposed model of AlGaN/GaN microwave power device is to demonstrate its inherent ability to operate at much higher temperature. An investigation of temperature model of a 1 μm gate AlGaN/GaN enhancement mode n-type modulation-doped field effect transistor (MODFET) is presented. An analytical temperature model based on modified charge control equations is developed. The proposed model handles higher voltages and show stable operation at higher temperatures. The investigated temperature range is from 100 °K–600 °K. The critical parameters of the proposed device are the maximum drain current (I_Dmax), the threshold voltage (V_th), the peak dc trans-conductance (g_m), and unity current gain cut-off frequency (f_T). The calculated values of f_T (10–70 GHz) at elevated temperature suggest that the operation of the proposed device has sufficiently high current handling capacity. The temperature effect on saturation current, cutoff frequency, and trans-conductance behavior predict the device behavior at elevated temperatures. The analysis and simulation results on the transport characteristics of the MODFET structure is compared with the previously measured experimental data at room temperature. The calculated critical parameters suggest that the proposed device could survive in extreme environments.     

45 nm CMOS technology with low temperature selective epitaxy of SiGe

This paper describes the advanced embedded silicon germanium (eSiGe) technologies to apply the 45 nm node CMOS fabrication technology. There are three key techniques as follows. The first technique is a low temperature of epitaxial growth at 550 °C to suppress staking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Σ)-shaped recess is applied, because the strain force on the channel of MOSFET is increased effectively by narrowing spacing between source and drain. The third one is to apply particular surface cleaning treatment before the epitaxial growth, to get the excellent SiGe crystallinity. We demonstrated the drain current of I_on = 725 μA/μm and I_off = 100 nA/μm for PMOSFET using above these techniques.     

Improvement of electrical properties of silicon-based thin-film transistors by modifying technological fabrication processes

This paper is a review of technological process evolution associated to electrical performance improvement of silicon-based thin-film transistors (TFTs) that were performed mainly in the GM/IETR laboratory. The main objective in agreement with the fields of applications is to fabricate TFTs at a temperature low enough to be compatible with the substrates, glass substrates in a first place and flexible substrates in a second one, which implies several approaches. In fact, the electrical properties of the TFTs, mainly field-effect mobility of carriers in the channel, I _on/I _off drain current ratio, and subthreshold slope, are strongly dependent on the quality and the nature of the channel material, on the material quality and thus on the density of states at the interface with the gate insulator, and on the quality of the gate insulator itself. All the improvements are directly linked to all these aspects, which means an actual combination of the efforts. For the glass substrate, compatible technology processes such as deposition techniques, or solid phase, or laser crystallizations of active layers were studied and compared. The paper details all these approaches and electrical performances. In addition, some results about the use of a silicon–germanium compound as channel active layer and airgap transistors for which the insulator is released, complete the presentation of the evolution of the silicon-based TFTs during the last twenty years.