基于注入锁定的RF低功耗正交本振信号产生电路

实现了一个基于注入锁定技术的射频低功耗正交本振信号产生电路.该电路由工作于两倍频频段的压控振荡器和两个注入锁定二分频器及缓冲器构成,可以为无线收发机提供正交本振信号.通过采用数字调谐技术,压控振荡器达到了很宽的调谐范围,而通过在注入锁定二分频器中加入与压控振荡器相同的变容管和电容阵列,保证了注入锁定二分频器在整个频带范围内都能保持锁定.该正交本振产生电路采用UMC 0.18 μm CMOS工艺实现.测试结果表明,在1.9～2.3 GHz频率范围内,该电路能够提供正交本振信号.该电路采用1.8 V电源供电,消耗的电流为2.2 mA(不包含缓冲器的电流),占用芯片面积为1.56 mm2.     

基于ADF4106的低相噪本振设计

为了实现低相噪的本振信号输出,本文设计出一种基于锁相环芯片ADF4106的低相噪本振源.通过实际调试,测试结果满足设计要求,并作为第二点频本振应用于一款通信测试仪器的中.     

高性能超低功耗的4.224GHz正交LC VCO

采用Jazz0.18μm RF CMOS工艺设计并实现应用于MB-OFDM超宽带频率综合器的4.224GHz电感电容正交压控振荡器。通过解析的方法给出了电感电容正交压控振荡器的模型,并推导出简洁的公式解释了相位噪声性能与耦合因子的关系。测试结果显示,核心电路在1.5V电源电压下,消耗6mA电流,频率调谐范围为3.566~4.712GHz;在主频频偏1MHz处的相位噪声为-119.99dBc/Hz,对应的相位噪声的FoM(Figure-of-Merit)为183dB;I、Q两路信号等效的相位误差为2.13°。     

一种2.4/3.2GHz正交锁相环的设计与实现

基于SMIC 65nm CMOS工艺,设计并实现了一款中心频率为2.4/3.2GHz的正交锁相环。该设计针对电源噪声,压控振荡器噪声等诸多问题进行了性能优化。经充分的仿真验证,锁相环的输出频率覆盖范围为2.14-3.97G Hz,正交VCO在1M Hz处的相位噪声为-106d B c,正交时钟相位误差仅0.5度,1.2V电压供压下功耗为20m W。     

一种2.4/3.2GHz正交锁相环的设计与实现

基于SMIC 65nm CMOS工艺,设计并实现了一款中心频率为2.4/3.2GHz的正交锁相环。该设计针对电源噪声,压控振荡器噪声等诸多问题进行了性能优化。经充分的仿真验证,锁相环的输出频率覆盖范围为2.14-3.97G Hz,正交VCO在1M Hz处的相位噪声为-106d B c,正交时钟相位误差仅0.5度,1.2V电压供压下功耗为20m W。     

一种Ku双本振多输出高频头的设计

高频头是一种数字卫星电视信号接收装置,它能对卫星接收信号进行变频和放大.介绍一种Ku双本振多输出高频头的工作原理、性能指标、仿真结果、技术难点、实测结果,并在工程实践中实现批量化生产.     

CMOS高频电流差分缓冲放大器

本文提出了一种利用修改的差分电流传输器(MDCC)与电压跟随器实现的全新高频CMOS差分电流缓冲放大器电路(CDBA).PSPICE仿真结果表明,在0～100MHz的频率范围内,提出的电路能很好地满足CDBA的端口特性.作为应用,实现了二阶电流模式多功能滤波器,并对他们进行了仿真.     

基于GaAs工艺的36GHz压控振荡器

利用法国OMMIC公司的0.2μm GaAs PHEMT工艺,设计实现了一个36GHz压控振荡器电路.该电路采用完全差分的调谐振荡器结构,通过引进容性源极耦合差动电流放大器和调谐负载电路,提高了电路的性能.测试表明:该压控振荡器中心频率为36GHz,调谐范围约为800MHz,在偏离中心频率10MHz处的单边带相位噪声为-98.83dBc/Hz.芯片面积为0.5mm×1mm,采用-5V单电源供电,核心单元功耗约为200mW.     

一个新结构低功耗2.5 GHz CMOS LC压控振荡器的设计

压控振荡器是锁相环电路的关键的组成部分之一,采用新的电流复用结构,可以明显降低该电路的功耗,而且由于没有尾电流,新结构还能有效改善电路的相位噪声.在TSMC 0.18 CMOS 1P6M工艺下的仿真结果表明:在1.25 V供电电压下振荡器的调节范围是2.26 GHz到2.76 GHz,在频偏1 MHz处的相位噪声为--130 dBc/Hz,平均功耗不超过1.2 mW.     

一种2.4GHz正交输出频率综合器

介绍了一种用于bluetooth的基于0.35μm CMOS工艺的2.4GHz正交输出频率综合器的设计和实现.采用差分控制正交耦合压控振荡器实现I/Q信号的产生.为了降低应用成本,利用一个二阶环路滤波器以及一个单位增益跨导放大器来代替三阶环路滤波器.频率综合器的相位噪声为-106.15dBc/Hz@1MHz,带内相位噪声小于-70dBc/Hz,3.3V电源下频率综合器的功耗为13.5mA,芯片面积为1.3mm×0.8mm.     

一种1.8V 0.8～2.1GHz直接变频CMOS正交下变频器

提出了一种CMOS宽带正交直接变频下变频器,片上集成了正交本振相位发生器.混频器采用三段式结构,包括跨导级、开关级和跨阻级作为输出级.跨导级采用互补型结构,在相同的功耗下获得更大的跨导.混频器核心电路未采用电感,能实现在宽频率范围内工作.芯片采用0.18μm CMOS工艺实现,整个变频器在1.8V电源电压下抽取29 m...     

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0.35μm CMOS technology are presented.A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals.A second-order loop filter,with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost.The measured spot phase noise is –106.15dBc/Hz@1MHz.Close-in phase noise is less than -70dBc/Hz.The synthesizer consumes 13.5mA under a 3.3V voltage supply.The core size is 1.3mm×0.8mm.     

一种相位精确可调的四路正交信号发生器

设计了一种相位精确可调的四路正交信号发生器,由相位精确调节器和二分频器构成。相位精确调节器通过控制尾电流源的导通产生可编程的电流,再使该电流转换成偏置电压叠加在时钟信号上,以此来调节二分频器产生的四路信号的相位差,使其相位精确互差90°。电路采用SMIC 0.13 μm CMOS工艺进行仿真验证。结果表明,在电源电压为1.2 V,偏置电流为7.2 μA,且电平信号的选通位数n=6时,产生的四路正交信号的误差精度可达±0.1°,调相范围达±3.6°。     

900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer

900 MHz CDMA, 1.8 GHz PCS, and 450 MHz CDMA RF receivers are implemented and measured. In order to reduce NRE cost and meet the demand of fast time-to-market, a metal-mask configurable method is applied for those receivers using only upper metals, contact and via layers. Also to reduce power consumption, a new mixer linearization method is proposed, along with an optimization methodology of an integrated inductor for a single balance mixer LO buffer, with respect to power consumption and silicon area. In order to apply the proposed inductor optimization methodology into metal-mask configurable circuits, inductor design considerations for metal-mask variant circuits are presented. With the proposed linearization technique and inductor optimization method, low power 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA mixers are obtained. The proposed receivers are fabricated in a 0.35 μm SiGe BiCMOS process. In the 900 MHz CDMA case, measurement results of the proposed mixer show 12 dBm IIP3 and 10.2 dB conversion gain, and 7.5 dB SSB NF with 10.5 mA current consumption at 2.7 V supply voltage.     

一种基于高压工艺的高精度电流采样电路

提出了一种用于大功率LED驱动芯片中的电流采样电路。采用电阻采样技术,运用高压、高增益、大带宽的运放,使采样电路具有高精度和快的响应速度。基于0.8μm 40 V BCD工艺,对提出的电流采样电路进行仿真验证。结果表明,在大功率应用下,该采样电路的采样精度高达99.68%,有很好的实用价值。     

基于ADF4113的本振源设计

应用美国ADI公司生产的数字分频器与鉴相器ADF4113和压控振荡器HE714构成锁相环。通过单片机AT89C51产生控制信号,设计了一个稳定的2 GHz本振源电路模块,应用于高频宽带线性调频源系统中。详细介绍了系统中核心芯片的性能、结构以及应用方法,设计出了完整的硬件电路并对电路的各个参数进行了评估。最后对电路产生的2 GHz本振信号进行仿真测试,结果基本上符合要求。     

基于常规芯片设计的波形合成电路

为了了解周期连续信号分解为若干谐波成分或由不同的谐波合成周期信号这一过程,采用常规芯片设计了一组简单电路,包括分频、滤波、放大、移相、加法器合成等电路。通过学生亲自动手搭接电路及观察各测试点信号分解和合成的过程,加深对周期连续信号分解与合成的理解。     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

A 4.8GHz CMOS Fully Integrated LC Balanced Oscillator with Symmetrical Noise Filter Technique and Large Tuning Range

This paper presents a fully integrated 4.8GHz VCO with an invention——symmetrical noise filter technique.This VCO,with relatively low phase noise and large tuning range of 716MHz,is fabricated with the 0.25μm SMIC CMOS process.The oscillator consumes 6mA from 2.5V supply.Another conventional VCO is also designed and simulated without symmetrical noise filter on the same process,which also consumes 6mA current and is with the same tuning.Simulation result describes that the first VCO’ phase noise is 6dBc/Hz better than the latter’s at the same offset frequency from 4.8GHz.Measured phase noise at 1MHz away from the carrier in this 4.8GHz VCO with symmetrical noise filter is －123.66dBc/Hz.This design is suitable for the usage in a phase-locked loop and other consumer electronics.It is amenable for future technologies and allows easy porting to different CMOS manufacturing process.