用户可重构系统芯片-U-SoC

随着深亚微米技术(DSM)的不断发展,完全专用的系统芯片(SoC)已经面临新的问题和挑战.本文在研究硅技术发展趋势、硅产品特征循环规律以及硅产业结构演变规律的基础上,提出了一种具有一定“通用“性的用户可重构系统芯片(UserreconfigurableSoC,简称U-SoC),它通过用户重构功能降低新产品的开发成本,缩短上市周期,提高设计效率,从而增强了SoC的适应性和灵活性.研究U-SoC设计方法,对于加速我国微电子产业的发展进程,实现跨越式发展有重要作用.     

用户可重构系统芯片—U—SoC

随着深亚微米技术（DSM）的不断发展，完全专用的系统芯片（SOC）已经面临新问题和挑战。本文在研究硅技术发展趋势，硅产品特征循环规律以及硅产业结构演变规律的基础上，提出了一种具有一定“通用”性的用户可重构系统芯片（User reconfigurable Soc,简称U-SoC)，它通过用户重构功能降低新产品的开发成本，缩短上市周期，提高设计效率，从而增强了SoC的适应性和灵活性。研究U-Soc设计方法，对于加速我国微电子产业的发展进程，实现跨越式发展有重要作用。     

可重构便携式多媒体通信终端

便携式多媒体通信终端产品将在未来几年内成为消费电子市场的主导，要求在现有的通信类终端产品基础上增强多媒体功能，从硬件结构到软件系统都需做出较大改进，文中在预测其硬件结构为可重构SoC的基础上．详细介绍了目前相关的硬件和软件方面的研究。     

可重构RF芯片相继问世

目前，以半导体厂家为中心，各个公司都在积极开发用一个芯片处理多个无线服务的多频带RF收发芯片。其目的在于通过将RF收发芯片与支持多协议的基带处理芯片集成在一起，开发出可利用手机网、WLAN室外热点，WiMAX等宽带无线服务、广播服务的终端。现在，美国的无线设计企业及大型半导体厂家正在开发可以收发4-5种无线频率、或可以自由转换收发频率的具有高附加值的多频带RF收发芯片。     

嵌入式可重构系统芯片的硬件验证平台设计

提出一种新的基于嵌入武可重构系统芯片的视频解码方案,采用了软硬件协同验证的方法.设计了相应的硬件验证平台,验证了H.264解码算法在可重构处理器上的可实现性.     

新型可重构结构能适应未来芯片集成度的提高

当前集成电路制造技术远远超过设计技术水平。现在单个芯片上能够提供的逻辑线路的门数,数量是如此众多,如何有效地充分利用这些门数,已经成为困扰计算机科研人员的一个难题了。何况新的制造技术还在继续层出不穷,原子规模级的开关线路虽然尚未成为现实,但是已经显示能够进一步提高芯片集成度的可能性。一旦成为现实,将进一步使这一个困扰设计人员的难题变得更加严重。近来出现了一种称为Cell Matrix（单元阵列）的新结构。看来这种新结构有可能解决这个困扰设计人员的难题。     

基于S-PIN二极管的频率可重构缝隙芯片天线研究

为了实现高度集成化的片上可重构天线系统,利用硅基固态等离子体表面PIN(S-PIN)二极管技术,设计了一种C—Ku波段频率可重构的领结型缝隙芯片天线。文中讨论了利用S-PIN二极管作为芯片天线频率可重构部件的设计标准,并对S-PIN二极管的结构参数进行了分析。通过控制S-PIN二极管的截止/导通状态,提出的缝隙芯片天线可以实现从6.7 GHz到17.97 GHz的工作频率可重构,增益分别为4.63 dBi和3.4 dBi。在实际的流片和测试过程中发现,文中研制的S-PIN二极管具有良好的伏安特性。此外,固态等离子体天线工作在C波段和Ku波段时的实际中心工作频点分别位于6.6 GHz和17.9 GHz,与仿真结果相比具有良好的一致性,验证了S-PIN二极管在制造频率可重构芯片天线方面的潜力。     

可重构技术在后SoC时代的应用——U—SoC

随着深亚微米(DSM)设计技术的发展和芯片设计复杂度的上升，完全专用的SoC系统面临新的问题和挑战，专家预测具有一定“通用”性质的系统芯片是后SoC时代的特征。本文在跟踪国际可重构技术的基础上，研究一种符合我国IC设计现状的用户可重构系统芯片，提出器件设计与应用设计分离的“片上创新应用”(Desipless)概念，并从硅技术发展规律的角度论述用户可重构系统芯片对硅产业结构下一轮分工的影响。     

可重构的SoC

可重构的SoC凭借在设计周期、成本等方面的优势，逐渐成为SoC发展的趋势。本文主要介绍了几种重构的设计方式。每种方法针对对象不同，可重构的范围和功能不同。在设计中，要从时间、花费、功耗、尺寸等方面综合考虑，选择合适的设计方法和设计结构，在开销尽可能少的情况下，保证设计和应用的最大灵活性。     

动态可重构技术打造更灵活的芯片

动态可重构是一种能够动态切换芯片电路结构的技术，目前，该技术正被越来越多地应用于各种设备中。例如，在复合机（MFP，Multi Function Peripheral）市场上，IPFlex公司是动态可重构技术的开创者，     

XiSystem: a XiRisc-based SoC with reconfigurable IO module

In the nanometer era, the increase in nonrecurring engineering costs is a challenge for SoCs that can be faced through a standardization process. Hardware specialization of a standard platform to a given application can be achieved by exploiting reconfigurable technology. This paper presents a XiSystem SoC, which integrates two different field-programmable devices to provide application-specific computing blocks and IOs. A XiRisc reconfigurable processor is exploited to achieve more than one order of magnitude speed-up and energy consumption reduction vis-a/spl grave/-vis a DSP-like processor, while an eFPGA is integrated in the system in order to make it flexible enough to support various IO ports and protocols. The reconfigurable IO device is also utilized for pre/post data processing and implementation of some standard computational blocks.     

Communication architecture design for reconfigurable multimedia SoC platform

Memory and communication architecture have a significant impact on the performance, cost, and power of complex multiprocessor system-on-chip designs. In this paper, we present an automated bus matrix synthesis flow for efficient transaction-level design space exploration of communication architecture in a reconfigurable multimedia system-on-chip platform. Specifically, we consider hardware interface selection problem, which has significant effect on the overall cost of area and power. We propose a method to solve such hardware interface selection problem through static analysis of communication behavior. We experiment with JPEG encoder and H.264 encoder examples and the results show the reduction of area by 56.91% and power by 48.61% of bus matrix with 0.58% performance overhead on average compared to the case of maximum performance. According to our HW interface selection algorithm, we also experiment MPEG4 video decoder example. And the result is evaluated on the FPGA prototyping board.     

Design of reconfigurable access wrappers for embedded core based SoC test

Testing of embedded core based system-on-chip (SoC) ICs is a well known problem, and the upcoming IEEE P1500 Standard on Embedded Core Test (SECT) standard proposes DFT solutions to alleviate it. One of the proposals is to provide every core in the SoC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a fixed test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers which allow for a dynamic change in the width of the TAM executing the core test. Analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Specifically, we derive a O(N/sub C//sup 2/B) time algorithm which can compute near optimal SoC test schedules, where N/sub C/ is the number of cores and B is the number of top level TAMs. Experimental results on benchmark SoCs are presented which improve upon integer programming based methods, not only in the quality of the schedule, but also significantly reduce the computation time.     

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip (SoC), which integrates switched-capacitor-based field programmable analog arrays (FPAA), analog-to-digital converter (ADC), digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit (CPU) and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7×8 mm² and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.     

SoC Emerging Technologies

Although silicon technology is continuously evolving to produce smaller systems with minimized power dissipation and at a lower cost and improved reliability, it is expected that this trend will have matured between 2014 and 2016. This will eventually lead to the integration of a multiplicity of technologies rather than simply silicon technology. This multiplicity of technologies will be the driving force to create unprecedented opportunities for realization of new integrated systems. The marriage of microelectronics and photon-based sciences with that of nanochemistry and biotechnology brings into the forefront the evolutionary progress in future SoC technology leading to intelligent systems-on-chip ( iSoCs) as the frontier of innovative products. iSoCs will enable the development of novel circuits and systems with extraordinary new properties relevant to nearly every sector of the economy. This integration, supported by a bio-based technology, provides the foundation for a future in which sensing, imaging, information processing, and communication can be integrated. New generations of auto-sensor health monitoring devices based on intelligent diagnostics such as intelligent pacemakers that respond to individual's activity needs, wearable sensors and smart communicators, etc., become part of an important "toolkit" to serve our aging population, leading to the emerging concept of iSoC as its fundamental building block. This evolutionary change is the result of revolutionary concepts that link microelectronics, photonics, nanochemistry, and biotechnology,-a crucial platform-bringing into the forefront the significance of iSoC technology as the future frontier of innovative research and related products.     

MCU/SoC

ATtiny48/88:picoPower tinyAVR微控制器Atmel推出两款新的低功耗32管脚tinyAVR微控制器——分别具有4kB和8kB闪存的ATtiny48和ATtiny88。这些AVR微控制器在1.8V和1MHz条件下仅消耗不到240μA     

高密度封装进展之三——SiP与SoC

哪种方式更能提高LST的附加值?是SiP(system in a package)还是SoC(system on a chip)?LSI厂家正对此进行激烈争论。作为系统集成的选择方式,LSI厂家一直集中力量致力于SoC的开发。但是LSI厂家发现,仅靠SoC这一条路线已不能满足用户的要求。目前,对于各大LSI厂家来说,要不要转换其发展资源的投入方向,需要当机立断。