无铅钎料电迁移可靠性研究进展

随着电子器件焊点尺寸及其间距的日趋减小,电流密度急剧增加,从而引发的电迁移可靠性问题更加显著。电迁移效应的发生,使得在阴极附近出现裂纹和孔洞,在阳极则产生小丘或堆积,从而导致电路短路或断路。介绍了近年来国内外关于无铅钎料合金包括SnAgCu、SnAg、SnZn和SnBi等电迁移研究,对实验的结果、特征及其方案进行了综述和评论。     

Effect of low k dielectrics on electromigration reliability for Cu interconnects

Multi-link statistical test structures were used to study the effect of low k dielectrics on EM reliability of Cu interconnects. Experiments were performed on dual-damascene Cu interconnects integrated with oxide, CVD low k, porous MSQ, and organic polymer ILD. The EM activation energy for Cu structures was found to be between 0.8 and 1.0 eV, indicating mass transport dominated by diffusion at the Cu/SiN_x cap-layer interface, independent of ILD. Compared with oxide, the decrease in lifetime and (jL)_c observed for low-k structures can be attributed to less dielectric confinement in the low k structures. An effective modulus B obtained by finite element analysis was used to account for the dielectric confinement effect on EM and found to correlate well with EM lifetime and the (jL)_c product of low-k interconnects.     

Sb掺杂对SnAgCu无铅焊点电迁移可靠性的影响

向Sn3.8Ag0.7Cu无铅焊膏中添加质量分数为1%的Sb金属粉末,研究了其焊点在电流密度为0.34×104A/cm2、环境温度150℃下的电迁移行为。通电245h后,阴极处钎料基体与Cu6Sn5IMC之间出现一条平均宽度为16.9μm的裂纹,阳极界面出现凸起带,钎料基体内部也产生了裂纹。结果表明:1%Sb的添加使焊点形成了SnSb脆性相,在高电流密度和高温环境下产生裂纹,缩短了焊点寿命,降低了电迁移可靠性。     

Shape effect on electromigration in VLSI interconnects

The influence of the shape of VLSI interconnects on the lifetime due to electromigration is investigated. Simulations and experiments indicate that, in some cases, the right angle corners of the metal lines, widely interconnections layout of VLSI circuits, reduce the lifetime of such interconnects. Substitutions by more gradual, smaller angled corners improve electromigration lifetimes.     

Skin effect of on-chip copper interconnects on electromigration

A simple model is derived to evaluate skin effect of on-chip copper interconnects on electromigration. The result gives the range of frequency in which skin effect on electromigration need to be taken into consideration.     

Effect of annealing on the surface microstructural evolution and the electromigration reliability of electroplated Cu films

This paper presents the effects of annealing, performed over a temperature range from 200°C to 400°C, on the surface microstructural evolution and the electromigration reliability of electroplated Cu films. After annealing, a substantial increase in surface roughness was observed, while variations in mean grain size and nanoindentation hardness were minor. Given the annealing temperature, the surface roughness was larger for the films annealed in forming gas, due to the existence of hydrogen. In particular, the films annealed at 400°C in forming gas demonstrated severe grain-boundary grooving and surface voiding. The defective nature of the annealed surface can be alleviated by chemical-mechanical polishing (CMP), when annealing is conducted prior to the CMP. However, it appears that a sequential thermal excursion at relatively high temperatures re-aggravates the integrity of the Cu surface. This argument may be supported by the electromigration-test results on dual-damascene interconnects fabricated using two different thermal profiles. The electromigration lifetimes were longer by more than a factor of two for the interconnects that skipped a post-passivation anneal at 400°C. The experimental evidence presented in this work suggests that controlling the integrity and quality of the Cu surface is an important step in ensuring good electromigration reliability.     

Study of the impact of electromigration on integrated circuit performance and reliability at design level

Electromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for the performance degradation. High values of temperature and current density accelerate the damage, causing an increase in the lines resistance and circuit lifetime reduction. In this work, a method is proposed to evaluate the electromigration effects in an operational amplifier circuit performance due the void growth induced by electromigration. The performance parameters are simulated by AC, DC and transient analysis for a specific temperature and time interval and the results are compared with a circuit free of electromigration. The method is used to investigate the circuit response regarding the unit gain frequency, voltage gain, cutoff frequency, output swing voltage and settling time. There are three lines that can be traditionally classified as critical due to the large current density they carry. Nevertheless, a fourth line, which has a current density below the maximum limit set by the technology being typically considered as non-critical from the layout design point of view, leads to significant reduction of the voltage gain and voltage swing, of about 59% and 14% in 5 years.     

Investigation of electromigration reliability of redistribution lines in wafer-level chip-scale packages

Wafer-level chip-scale packages (WLCSPs) have become subject to the same drive for miniaturization as all electronic packages. The I/O count is increasing and ball pitch is shrinking at the expense of trace pitch and in turn, current densities are increasing. This leads to current crowding and Joule heating in the vicinity of solder joints and under bump metallurgy (UBM) structures where resistance values change significantly. These phenomena are responsible for structural damage of redistribution line (RDL)/UBM and UBM/solder interconnects due to ionic diffusion or electromigration. In this work, sputtered Al and electroplated Cu RDLs were examined and quantified by three-dimensional electrothermal coupling analysis. Results provide a guideline for estimating maximum allowable currents and electromigration lifetime.     

Calibration of electromigration reliability of flip-chip packages by electrothermal coupling analysis

Electromigration reliability of solder interconnects is dominated by current density and temperature inside the interconnects. For flip-chip packages, current densities around the regions where the traces connect a solder bump increase significantly due to the differences in feature sizes and electric resistivities between the solder bump and its adjacent traces. This current-crowding effect along with induced Joule heating accelerates electromigration failures. In this paper, the effects of current crowding and Joule heating in a flip-chip package are examined and quantified by three-dimensional electrothermal coupling analysis. We apply a volumetric averaging technique to cope with the current-crowding singularity. The volumetrically averaged current density and the maximum temperature in a solder bump are integrated into Black’s equation to calibrate the experimental electromigration fatigue lives. An erratum to this article is available at .     

Lateral interface effect on pulsed DC electromigration analysis

DC and Pulsed DC Electromigration tests at 1Hz and lOkHz have been performed on two single level Al-0.5%Cu metallizations. The Black's parameters have been analysed with a great confidence level using a statistical global approach. The results are in agreement with the Average Current Model at 10kHz and with the On-Time Model at 1Hz considering that thermal effects not only affect the current density exponent n, but also the duty cycle accelerating factor m. The extracted activation energies reflect the same diffusion mechanisms for the two metallizations. Microscopic observations showed huge metal accumulations for each structure and emphasized the influence of the resist stripping stage on the electromigration behaviour of the samples.     

Influence of thermal heating effect on pulsed DC electromigration

Pulsed DC Electromigration (EM) tests up to 1MHz have been performed on single level Al-0.5%Cu metallization. The results are in good agreement with an Average Current Model when the thermal heating effect has been corrected with an original thermal model. Thus, Median Time to Failure (MTF) increase in the MHz region also reported by some authors, appears as a thermal effect. Furthermore, SEM observations showed very large metal accumulations and hillocks which were not seen in DC experiments.     

高温恒定电流电迁移可靠性试验及结果分析

介绍了评价电迁移可靠性的高温恒定电流试验方法,以电阻值超过初始值10％为失效判据,对某工艺的几组样品进行可靠性评价。该试验方法简便、可靠,适用于亚微米和深亚微米超大规模集成电路的可靠性评价。     

Copper electromigration modeling including barrier layer effect

Electromigration lifetime considering the barrier layer effect under the DC and pulsed DC stress is analyzed numerically. The barrier layer used to stop the copper diffusion also improves the interconnect lifetime. The improvement of lifetime under the DC stress is higher than that under the pulsed DC stress. The lifetime model predictions are also compared with experimental data. Good agreement between the model predictions and experiments is obtained.     

Effects of deposition conditions of Al and Ti underlayer on electromigration reliability for deep-submicron interconnect metallization

We have studied the effects of Ti underlayer (collimated Ti vs. standard Ti) and Al deposition power (12 KW vs. 6 KW) on the electromigration (EM) lifetime of bottom-Ti/Al-0.5wt.%Cu/Ti/TiN-top stack. The (002) texture of standard Ti (s-Ti) was stronger than that of collimated Ti (c-Ti). The Al stack prepared with s-Ti underlayer, which had the stronger Al (111) texture and more uniform grain size distribution, showed better EM lifetime than the same with c-Ti underlayer, independent of the Al deposition power. The Al stack prepared with an Al deposition power of 6 KW was also found to show better EM lifetime than the same with a 12 KW deposition power, independent of the type of Ti underlayer. Longer deposition time for low power sputtering resulted in the stronger Al (111) texture, larger median grain size, and more uniform Ti−Al reaction layer. Finally, the effects of Ti underlayer and Al deposition power on the EM lifetime of Al-0.5%Cu films could be well explained by the grain size distribution and Al (111) texture, which is closely related to the underlying-Ti (002) texture.     

Bulk electromigration reliability tests of large-grained aluminum lines with regard to semiconductor contacts

A test structure was devised for investigating electromigration reliability. Considering electromigration threshold, narrow large-grained Al/Si interconnect lines failed on contacts due to homogeneous bulk electromigration. Failure times were dependent on the uniformity of the contact interfaces. Bulk electromigration was marked by an extremely low mass flow at the test temperature of 200°C. This mass flow will be reduced considerably with decreasing temperature due to the activation energy of 1.38 eV. Si electromigration can damage pn-junctions. A double layer metalization, like annealed Ti-Al, may delay or prevent Si mass flow, but a strong interface electromigration occurs. Comparable double layers are improper for future integrated circuits. The advantage of bulk electromigration is not restricted to narrow lines. Wide lines have to be divided into separated sections, which behave like narrow, large-grained lines.     

Computational analysis of the interfacial effect on electromigration in flip chip solder joints

Recent experiments have shown failure in flip chip micro solder joints induced by electromigration. This paper proposes a three-dimensional computational model to simulate the evolution of micro and sub-micro scale solder joints due to electromigration induced diffusion. The evolving morphology of the solder joint related with multiple mechanisms causes a computational challenge. This is addressed by employing a diffuse interface model with multiple concentrations. To efficiently resolve complications, a semi-implicit Fourier spectral scheme and a biconjugate-gradient method are adopted. Results have demonstrated rich dynamics and solder breakage at the interface on the cathode side. Furthermore, the effect of the designed interface region on the reliability of solder joints has been investigated with the developed model.     

Width dependence of the effectiveness of reservoir length in improving electromigration for Cu/Low-k interconnects

Reservoir effect of electromigration (EM) reliability has been investigated in Cu/low-k dual-damascene interconnects with varied reservoir lengths. However, the effectiveness of the reservoir effect in improving EM reliability as a function of line width has not been studied till now. In this work, experimental studies of the reservoir effect for both narrow and wide metal lines are conducted. It is found that the reservoir effect is more effective for a narrow line. The variation of the reservoir effectiveness as a function of the reservoir length is found to be different for different line width, and atomic flux divergence (AFD) distribution in the interconnect is used to explain the experimental results with good agreement.     

Modeling the effect of reliability on performance

In many high-reliability systems, subsystem or component failures that do not cause a system failure can still degrade system performance. When modeling such systems, ignoring the effect of reliability on performance can lead to incomplete or inaccurate results. In the present work, performability modeling, the combined analysis of reliability and performance, is introduced; some examples of applications where performance and reliability need to be modeled together are given; a strategy for modeling the effect of reliability on performance is outlined and metrics that help quantify this effect are discussed. Some mathematical models for performability are introduced and an example is used to illustrate how such models can be applied     

Resistance decay after electromigration as the effect of mechanical stress relaxation

Resistance decay has been observed in Aluminum narrow lines when the high stressing current in electromigration tests is turned off. It has been interpreted as the consequence of the relaxation of electromigration-induced mechanical stress.