A transformer with high coupling coefficient and small area based on TSV

Transformer is an important passive device, which is widely used in radio frequency (RF) Integrated circuit (IC). In this paper, three-dimensional transformers with turn ratios of 1:1, 1:2, and 1:3 and with primary and secondary windings nested by TSV technology is proposed. To evaluate the characteristics, the proposed transformers are simulated by HFSS software. The simulation results show that their coupling coefficients are 0.966, 0.966, 0.967, and their area are 3.6 × 10⁻³, 6.0 × 10⁻³, 9.6 × 10⁻³mm². Compared with the other literature, the proposed transformers have good coupling and small area.     

基于高阻硅的毫米波IPD 滤波器研究

5G 通信迫切需要毫米波集成无源器件(Integrated Passive Device,IPD),要求该类器件低成本、高性能。基于高阻硅(High Resistivity Silicon, HRS)工艺设计并加工了一款四阶交叉耦合毫米波微带滤波器,基于测试结果和有耗耦合矩阵理论反提取得到四阶滤波器谐振器的真实无载品质因素。进而对高阻硅基的毫米波工艺参数(例如,损耗角正切)进行修正,利用电磁仿真软件进行验证;分析了金属粗糙度对于滤波器损耗的影响。修正后的模型仿真结果和测试结果吻合较好,验证了修正后毫米波段高阻硅基参数的有效性,为芯片级毫米波无源器件的设计提供了支撑。     

基于PEN柔性衬底的顶发射微腔OLED性能研究

设计了结构为Ag/MoOx空穴注入层(HIL)/有机层/LiF/Al/Ag/Alq3的柔性有机电致发光器件(FOLED),研究通过改变HIL层的厚度改变腔长实现对微腔效应的调节,制备了性能优化的微腔FOLED。通过器件性能的对比,得到了可用Ag作为反射阳极的顶发射微腔FOLED全彩显示器件优化结构,即蓝、绿和红FOLED对应的优化HIL层厚度分别为100nm、120nm和160nm。     

薄膜衬底电极CNT阴极制备及场发射性能研究

采用电泳沉积(EPD,electrophoretic deposition)法在不同薄膜衬底电极上制备碳纳米管(CNT,carbon nanotube)场发射阴极.采用场发射扫描电子显微镜(FESEM)对其进行表面形貌表征,结果表明,EPD可以制得CNT均匀分布的场发射阴极.场发射测试结果表明衬底电极对CNT阴极的场发...     

The effects of substrate bias,substrate temperature,and pulse frequency on the microstructures of chromium nitride coatings deposited by pulsed direct current reactive magnetron sputtering

Recently, great attention has been devoted to the pulsed direct current (DC) reactive magnetron sputtering technique, due to its ability to reduce arcing and target poisoning, and its capability of producing insulating thin films. In this study, chromium nitride (CrN) coatings were deposited by the bipolar symmetric pulsed DC magnetron reactive sputtering process at different pulse frequency, substrate bias voltage, and the substrate temperature. It was observed that the texture of CrN changed from (111) to (200) as substrate temperature increased to 300°C as deposited at 2 kHz without substrate bias. With increasing pulsing bias and pulse frequency of target, predominated (200) orientation of CrN film was shown due to the ion bombardment/channeling effect to preferentially sputter those unaligned planes. For the CrN coatings deposited with pulsed biasing, the grain size decreased with increasing pulse frequency and substrate bias, whereas the surface roughness showed a reverse trend. The deposition rate of the CrN films decreased with increasing pulse frequency. It was concluded that the pulse frequency, substrate bias, and substrate temperature played important role in the texture, microstructure, and surface roughness of the CrN coatings deposited by the pulsed DC magnetron sputtering process.     

Preparation of silica/ceria nano composite abrasive and its CMP behavior on hard disk substrate

A novel silica/ceria nano composite abrasive was synthesized by homogeneous precipitation using carbamide, ammonium ceric nitrate and silica. The abrasive was characterized by X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), time-of-flight secondary ion mass spectroscopy (TOF-SIMS) and scanning electron microscopy (SEM), respectively. Then, the chemical mechanical polishing performances of the composite abrasive on hard disk substrate with nickel-phosphorous plated were investigated. Atomic force microscopy images show that the prepared abrasive gives much lower topographical variations than before polishing. The average waviness (Wa) of the polished hard substrate surface can be reduced from 15.5 Å before polishing to 8.36 Å, and the average of roughness (Ra) can be reduced from 14 Å before polishing to 4.80 Å.     

The effects of process conditions and substrate on copper MOCVD using liquid injection of (hfac)Cu(vtmos)

Copper MOCVD (metalorganic chemical vapor deposition) using liquid injection for effective delivery of the (hfac)Cu(vtmos) [1,1,1,5,5,5-hexafluoro-2,4-pentadionato(vinyltrimethoxysilane) copper(I)] precursor has been performed to clarify growth behavior of copper films onto TiN, <100> Si, and Si₃N₄ substrates. Especially, we have studied the influences of process conditions and the substrate on growth rates, impurities, microstructures, and electrical characteristics of copper films. As the reactor pressure was increased, the growth rate was governed by a pick-up rate of (hfac)Cu(vtmos) in the vaporizer. The apparent activation energy for copper growth over the surface-reaction controlled regime from 155°C to 225°C was in the range 12.7–32.5 kcal/mol depending upon the substrate type. It revealed that H₂ addition at 225°C substrate temperature brought about a maximum increase of about 25% in the growth rate compared to pure Ar as the carrier gas. At moderate deposition temperatures, the degree of a <111> preferred orientation for the deposit was higher on the sequence of <Cu/Si<Cu/TiN<Cu/Si₃N₄. The relative impurity content within the deposit was in the range 1.1 to 1.8 at.%. The electrical resistivity for the Cu films on TiN illustrated three regions of the variation according to the substrate temperature, so the deposit at 165°C had the optimum resistivity value. However, the coarsened microstructures of Cu on TiN prepared above 275°C gave rise to higher electrical resistivities compared to those on Si and Si₃N₄ substrates.     

保护环版图结构对ESD防护器件耐压能力的影响

基于华润上华0.5 μm双极-CMOS-DMOS (BCD)工艺设计制备了不同保护环分布情况下的叉指型内嵌可控硅整流器的横向扩散金属氧化物半导体(LDMOS-SCR)结构器件,并利用传输线脉冲(TLP)测试比较静电放电(ESD)防护器件的耐压能力.以LDMOS-SCR结构为基础,按照16指、8指、4指和2指设置保护环,形成4种不同类型的版图结构.通过器件的直流仿真分析多指器件的开启情况,利用传输线脉冲测试对比不同保护环版图结构的耐压能力.仿真和测试结果表明,改进后的3类版图结构相对于普遍通用的第一类版图结构,二次击穿电流都有所提升,其中每8指设置一个保护环的版图结构二次击穿电流提升了76.36％,其单位面积的鲁棒性能也最好,为相应工艺设计最高耐压值的ESD防护器件提供了参考结构和方法.     

基于IC产品分档的成品率与效益协调优化设计方法

文章在对IC产品按性能优劣分档的基础上，构造了一个既能体现IC产品的性能优劣和价格大小，又可根据各档次IC产品的市场价格进行调节的性能价格函数：Ep(X)=-1pln{e^-p ∑Mi=1e^P(kiΦi(x)-α)}，从而建立了成品率与效益协调优化模型：maxX^0YE(X^0)=∫R^aEp(X)P(X,X^0)dX。     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.     

Impact of injection limitations on the contact resistance and the carrier mobility of organic field effect transistors

The contact resistance as well as the mobility have developed to key performance indicators for benchmarking organic field-effect transistors. Typically, conventional methods for silicon transistors are employed for their extraction thereby ignoring the peculiarities of organic transistors. This work outlines the required conditions for using conventional extraction techniques for the contact resistance and the mobility based on TCAD simulations and experimental data. Our experimental data contain both staggered and coplanar structures fabricated by exploiting different optimization techniques like SAM treated electrodes, different shearing speeds, PS blending and silicon oxide functionalization. In addition, the work clarifies how injection limited current–voltage characteristics can affect high-performance organic field-effect transistors. Finally, we introduce a semi-physical model for the contact resistance to accurately interpret extracted benchmark parameters by means of the transfer length method (TLM). Guidelines to use conventional extraction techniques with special emphasis on TLM are also provided.