DESIGN OF POLYPHASE WAVE DIGITAL FILTERS WITH APPROXIMATELY LINEAR PHASE

It is well known that IIR digital filters require quite fewer computations,comparedwith FIR filters,in order to meet stringent magnitude specifications when the phase distortioncan be tolerated.An approximately linear phase,however,can be also obtained with the IIRfilter by making use of a technique without increasing the complexity.Based on a certain numberof attenuation zeros in the pass band,a new approach is developed for the design of polyphasewave digital filters with exact magnitude responses and Chebyshev approximation of the desiredphase responses.The minimum number of attenuation zeros is estimated,and some examples areincluded.     

一种高效数字滤波器结构及其灵敏度分析

本文基于矩阵分解,提出了一种新的数字滤波器结构,并导出了其传递函数的灵敏度表达式。该结构实际上是文献[10]中提出结构的改进型,比后者更加简单,易于实现。同时,本文对此结构同传统的几个主要结构进行了性能上的比较。仿真结果表明,同经典最佳结构相比,新结构抵抗有限字长误差的能力与其非常接近,但由于结构的简洁性,新结构在实时信号处理中具有更大的实用价值。     

基于FPGA的FIR滤波器的性能研究

目前FIR滤波器的一般设计方法比较繁琐,开发周期长,如果采用设计好的FIR滤波器的IP核,则开发效率大为提高。本方案基于Altera公司的Cyclone Ⅱ系列芯片EP2C8Q208C8N,首先利用MATLAB中的滤波器函数fir2得出需产生的FIR滤波器的系数,再导入FIR IP Core,成功完成了FIR数字滤波器的设计。另外分析了阶数与不均匀采样数据对FPGA资源的影响和对生成FIR滤波器的输出性能的影响,并将实际输出的幅频特性图与我们需要的幅频特性图相比较,验证生成的FIR数字滤波器的性能。     

Research of sub-channel filter technique in the digital channelization

In the satellite communications,there were very high performance requirements for the satellite transponder due to the restrictions of the volume and weight of the load,and the satellite channelization technique was an important means to solve this problem.The overall implementation structure and the sub-channel filter design method which played a serious role in the system were discussed.It has important practical significance to the overall implementation of the digital channelization.     

数字滤波器组在多载波调制中的应用

介绍了用数字滤波器组实现多载波调制的原理、性能以及可能的研究方向,重点比较了用数字滤波器组实现多载波调制与用DFT实现多载波调制的性能,并给出了仿真结果。     

Improving wave digital simulation by extrapolation techniques

Wave digital simulation principles are known to exhibit excellent numerical stability properties due to their inherent passivity. Yet, the achievable accuracy may not suffice in all applications. In this paper, it will be discussed how extrapolation techniques known from numerical mathematics can be merged with the wave digital concept. The proposed techniquecan be applied to both ordinary and partial differential equations. Astwo examples will show, high numerical accuracy can be obtained this way withoutsacrifycing passivity and the advantageous properties induced by the latter.     

基于人工鱼群算法的IIR数字滤波器设计

将人工鱼群算法（AFSA）用于IIR数字滤波器设计，建立了相应的优化模型，给出了简化的人工鱼群算法及其实现步骤。最后，将该算法用于低通、带通IIR数字滤波器的设计，并与粒子群算法进行了比较。仿真结果证明了AFSA的有效性，并且具有算法灵活、简单，全局收敛性好。收敛速度快的优点。     

一种单片机数据采集系统的数字滤波器设计

单片机数据采集系统在单片机自动测量、自动控制等领域具有广泛的应用,在数据采集环境,不可避免地将要产生各种各样的干扰和破坏,造成信号突变或中断,进而影响采集数据的正确性和精确性,造成控制错误等严重后果。因此研究单片机采集系统的抗干扰技术,是单片机应用技术的重要一环。文中采用数字滤波实现单片机的抗干扰技术,结合使用多种滤波算法,达到既消除高频干扰,又避免脉冲干扰的目的。     

数字频率特性测试仪的设计

传统的模拟式频率特性测试仪存在价格昂贵、条件苛刻、操作不便和性能指标易受温漂因素影响等不足。针对以上缺点,通过采用数字技术,将先进的 DDS 和 MSP430单片机相结合,集合一些常用的外围模拟电路,设计了一个简易的频率特性测试仪。系统对待测电路的输入信号及其输出响应采样,经数字信号处理后,获得电路的幅频特性和相频特性。设计的测试仪测某RLC网络,中心频率的相对误差小于0.2%,有载品质因数相对误差小于1.25%,最大电压增益大于-1 dB。频率特性测试仪输入输出阻抗均为50Ω,幅频误差绝对值小于0.5 dB,相频误差绝对值小于3°。测试仪能满足一般测试参数需求。     

An approach to the hardware implementation of wave digital filters

An approach to implement wave digital filter is presented. The implementation method is applicable to wave digital filters containing only 3-ports adaptors, connected with reflection-free ports. All arithmetic operations are performed in a special arithmetic unit. Main features are the fact that the arithmetic units are effectively utilized, and that only a few memories of standard type are needed.     

基于频域滤波数字均衡器的设计

为了解决多频段数字均衡滤波器处理过程中数据计算量的问题,通过对数字均衡器设计的分析,将数字音频信号进行频域滤波处理,最终设计出一种高效的数字均衡滤波器。通过将数字信号在频域中进行傅里叶变换,提出了一种基于快速傅里叶变换原理的算法,该算法中码位倒置和蝶形运算方法的处理与通常的快速傅里叶变换相比,更有效地减少了数据的运算量,减少了数据处理的时间。结果表明,使用该种算法设计的数字均衡滤波器与传统的时域滤波方法相比,具有很好的实时处理效果。     

Mapping 3-D IIR digital filter onto systolic arrays

We present here an efficient systolic implementation for 3-D IIR digital filters. The systolic implementation is obtained by using an algebraic mapping technique. This new mapping technique gives us the choice to mix pipelined variables and broadcast variables. We also determine, through the mapping method, the buffer sizes, the direction of variables propagations and the data feeding and extracting points. The resultant systolic array implementation is a modular structure composed of 2-D filter modules connected by simple buffers. This new systolic implementation is regular, modular and amenable to VLSI Implementation.     

一种Farrow结构数字延时滤波器的设计

普通数字延时滤波器虽然结构简单,但系数计算过程复杂,在延时参数快速变化时,系数更新速度无法满足实时性要求,在工程应用上受限制。采用Farrow结构数字延时滤波器能够更加灵活高效地进行分数延时滤波,延时参数改变时,无需重新计算滤波器系数,更容易在现场可编程门阵列(FPGA)上实现。介绍了一种Farrow结构数字延时滤波器,提出采用基于对称结构的滤波器系数求解方法,并经过加权优化,获得最终Farrow滤波器的系数。系数计算过程中,通过对设计所得Farrow滤波器延时精度和误差的分析,调整加权因子的取值和滤波器阶数,进而提高延时精度。计算机仿真结果证明了加权对称系数求解Farrow滤波器系数方法的有效性和实用性。     

基于免疫算法的IIR数字滤波器优化与实现

由于IIR数字滤波器设计实质上是一个非线性高维复杂函数优化问题,文中提出基于具有全局搜索能力强,收敛速度快特点的免疫算法实现IIR数字滤波器优化设计的新方法,给出了IIR滤波器优化设计的数学模型,描述了应用免疫算法优化设计IIR数字滤波器的具体实现步骤。通过低通和高通IIR数字滤波器设计的仿真结果表明方法的有效性和高效性。     

基于FPGA的FIR数字滤波器设计与实现

简要介绍了FIR数字滤波器的结构特点和基本原理,提出基于FPGA和DSP Builder的FIR数字滤波器的基本设计流程和实现方案。在Matlab/Simulink环境下,采用DSP Builder模块搭建FIR模型,根据FDATool工具对FIR滤波器进行了设计,然后进行系统级仿真和ModelSim功能仿真,其仿真结果表明其数字滤波器的滤波效果良好。通过SignalCompiler把模型转换成VHDL语言加入到FPGA的硬件设计中,从QuartusⅡ软件中的虚拟逻辑分析工具SignalTapⅡ中得到数字滤波器实时的结果波形图,结果符合预期。     

基于单自由度振动模型的IIR数字滤波器设计

无限冲击响应(IIR)数字滤波器设计通常需要先设计S域滤波器,再变换到Z域。为简化IIR数字滤波器的设计过程,本文提出利用单自由度系统(SDOF)模型直接设计IIR数字滤波器的方法,包括低通、带通、高通、带阻等。仿真结果表明设计过程直接、简单,滤波器参数不需要随采样频率而变,具有良好特性,是一种设计IIR数字滤波器的简便易用的新方法。     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能．在Xilinx ISE10．1开发平台中,采用VerilogHDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构。并在ModelSim仿真验证平台中仿真了实现设计。结果表明,改进串行结构的实现消耗资源少但滤波速度慢．并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少。     

A reconfigurable OTA-C baseband filter with wide digital tuning for GNSS receivers

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μm RFCMOS process is proposed.The filter can be configured as a complex band pass filter or two real low pass filters.An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations.An extended tuning range(above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques.In the complex band pas...     

GNSS接收机中可配置式宽范围数字调谐OTA-C滤波器

The design of a digitally-tunable sixth-order reconfigurable OTA-C filter in a 0.18-μ m RFCMOS process is proposed. The filter can be configured as a complex band pass filter or two real low pass filters. An improved digital automatic frequency tuning scheme based on the voltage controlled oscillator technique is adopted to compensate for process variations. An extended tuning range (above 8:1) is obtained by using widely continuously tunable transconductors based on digital techniques. In the complex band pass mode, the bandwidth can be tuned from 3 to 24 MHz and the center frequency from 3 to 16 MHz.     

基于MATLAB与FPGA的FIR滤波器设计与仿真

数字滤波器是数字信号处理领域内的重要组成部分。FIR滤波器又以其严格的线性相位及稳定性高等特性被广泛应用。本文结合MATLAB工具软件介绍了FIR数字滤波器的设计方法,并在Xilinx的FPGA器件上完成设计实现。最后,使用MATLAB和ModelSim软件对数据进行了分析,证实了设计实现的正确性与可行性。