Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO₂ gate dielectric.     

Effects of moisture and elevated temperature on reliability of interfacial adhesion in plastic packages

The interfacial-adhesion performance between the lead frame and molding compound was studied after temperature cycles and hygrothermal aging, simulating a typical package-assembly process. The hygrothermal aging involved a treatment at 85°C and 85% relative humidity (RH) for 168 h and three cycles of infrared (IR) solder-reflow condition. The interfacial-bond strengths were measured using shear and lead-pull tests. The lead-frame surface finishes studied include a bare Cu, microetched Cu, spot Ag coating, Ni, Pd/Ni, and Au/Ni coatings. Special emphasis was placed on the study of the changes in surface characteristics and the corresponding interfacial adhesion after various manufacturing processes. It was found that moderate thermal cycles enhanced the interfacial adhesion for all coated lead frames, except the Ni coating. Hygrothermal aging was detrimental to the interfacial-bond strength, especially for hydrophilic or polar surfaces, such as bare Cu, Ag, Pd/Ni, and Au/Ni coated lead frames. The introduction of tiny dimples etched on the lead frame was effective in mitigating the reduction in interfacial-bond strength arising from hygrothermal aging. This result confirms the important role of the mechanical-interlocking mechanism provided by dimples in retaining the interfacial adhesion in a humid environment.     

Impact of pre-conditioning, voltage bias and temperature on reliability of plastic encapsulated microcircuits

This paper investigates the effect of pre-conditioning, voltage bias and test temperature on the reliability of DIP and SOIC packages, molded with four different epoxy compounds, which were subjected to accelerated test conditions.     

Design concept for wire-bonding reliability improvement by optimizing position in power devices

The most effective way to increase the reliability of wire bonds in IGBT modules is reduction of temperature difference between the aluminum wires and the device. However, this lowers the power handling capability of the modules. In this paper, we show that the configuration of aluminum wire bonds on power devices has a considerable effect on the temperature distribution of the device, and that the optimization of the layout by thermo-electric simulation can make the temperature distribution of the devices more uniform and consequently reduce the maximum junction temperature difference, ΔT_jmax. Tentative experiments showed that rearranging the bonding position resulted in reduction of ΔT_jmax by five to 8 °C, and that the chip temperature distribution estimated by the thermo-electric simulation was qualitatively similar to the actual measurement results. These results suggest that wire-bonding optimization by thermo-electric simulation can contribute not only to realizing more compact power modules but also to improving the module reliability.     

晶体管封装腔内水汽含量的分析与控制

本文在对现有国军标晶体管封装腔内水汽含量检测及分析的基础上,提出了降低腔内水汽含量的有效办法和途径,经改进封装后的国军标晶体管,其腔内水汽含量从原来的27300－26200PPm下降到274－542PPm,改善了将近两个数量级,大大低于GJB33A－97规定的500PPm的标准要求,器件可靠性的提高,必将为广大军用户重点国防工程,军事装备的系统可靠性创造美好的前景。     

Influence of temperature, humidity, and defect location ondelamination in plastic IC packages

The modified J-integral and the stress intensity factor based on linear elastic fracture mechanics can be applied to predict the growth of interfacial delamination in integrated circuit (IC) packages. One of the key parameters required is the interfacial fracture toughness. This paper describes the measurement of the interfacial fracture toughness as a function of temperature and relative humidity using a three-point bending test. The interfacial fracture toughness was found to decrease with temperature and relative humidity. It is proposed that delaminations propagate from very small voids or defects present at the interface. The effect of the location of these interfacial defects or cracks on delamination was studied. The IC package evaluated in this paper was an 80-pin quad flat package with a 0.2 mm defect or crack at the edge or at the center of the interface. It was found that as the temperature of the package was increased, the stress intensity factor of the edge crack was higher than that of the center crack. However, whether the edge crack will propagate first as temperature is increased depends on the ratio of mode II interface toughness to that of the mode I interface toughness. For the package under investigation, it was established that when this ratio is less than 2.69 the edge crack would propagate first, otherwise the center crack would. For small defects, it was found that the water vapor pressure developed at the interface did not have a significant effect on the value of the crack-tip stress intensity factor     

Warpage in plastic packages: effects of process conditions, geometry and materials

The effects of several important parameters, including processing conditions, package geometry and materials, are specifically studied on the occurrence of warpage and coplanarity for a plastic package. Special emphasis is placed on the evaluation of moulding compound properties and optimal processing conditions that can effectively minimize warpage. It is found that moulding compounds requiring a low moulding temperature and having a low coefficient of thermal expansion (CTE) can significantly reduce warpage. The elastic modulus was found to be inversely proportional to warpage, indicating the modulus should be kept as high as possible. The post-mould curing is essential to reducing warpage as it increases the glass transition temperature, but lowers the thermal shrinkage. A cross-shaped die paddle against a full square paddle, a thick die attach and a large die size are also favorable to reducing warpage.     

How well can we assess thermally driven reliability issues in electronic systems today? Summary of panel held at the Therminic 2002

A panel was organized at the Therminic 2002 workshop to address the question posed in the title of this summary paper. Brief presentations were made by the six panelists, followed by an open discussion among Workshop participants. The focus of the panel was on reliability, not performance, and on systems, not parts. While the panel recognized the availability of various specialized analytical tools at a handful of leading research institutions and with expert individuals, it was felt that the industry at large is still transitioning from the use of simple thermal design rules to a more detailed physics based methodology. The current state-of-the-art of thermal metrology was outlined. An overview of the temperature-reliability relationships at the component and system levels was provided. Some of the emerging thermal challenges associated with the evolution of three-dimensional on-chip interconnect architectures were identified. The role of uncertainty analysis in predictions was emphasized. A primary conclusion was to focus on the prediction of thermally influenced risks in current and future products, based on a sound physics based approach.     

Effects of dimple and metal coating on interfacial adhesion in plastic packages

This paper reports on the effects of dimple and metallic coating of the Cu-alloy lead frame on interfacial adhesion with an epoxy-molding compound. Round dimples of varying number are introduced on one side of the lead frame by chemical etching. The plating materials studied include bare-Cu alloy and microetched Cu, Ag, Ni, Pd/Ni, and Au/Ni coatings. The surface characteristics, such as wettability, surface roughness, and element compositions, were evaluated based on several characterization tools, which, in turn, are correlated with adhesion performance. The dimples enhanced the interfacial-bond strengths through improved mechanical interlocking of the molding compound, depending on the type of coating. The improvement was much more significant for the coatings with inherently weak interfacial adhesion (e.g., microetched Cu and Ni coating) than those with inherently strong adhesion characteristics (e.g., Au and Pd coatings). The wettability of the metal surface represented by the surface energy or interfacial energy played a dominant role in the resulting interfacial adhesion. Elemental analysis of the fracture surface indicates that the silicon content had roughly a linear relationship with the interfacial-bond strengths for different coatings. The surface roughness was insensitive to the interfacial-adhesion performance. The silicon content measured from the lead-frame fracture surface was shown to directly correlate to the interfacial-bond strength. Higher silicon content was a reflection of larger surface-area coverage by the molding compound associated with cohesive failure.     

微波炉功率,均匀性及安全性的测定

本文用国际电工委员会(IEC)建议的方法对市场上几种常见类型家用微波炉的输出功率、均匀性及安全性进行了更仔细的测定.由我们的工作得出结论:测量微波炉功率时,用2000g水作为负载较为合适,且负载面积应占腔体底面积的16%以上,此时测出的功率更准确和接近标称功率,而测定微波炉漏能时则应使用较小负载.转盘转动时负载的受热均匀性较转盘静止时提高约1倍.     

Design,development and reliability testing of a low power bridge-type micromachined hotplate

In this paper, the development and reliability of a platinum-based microheater with low power consumption are demonstrated. The microheater is fabricated on a thin SiO₂ bridge-type suspended membrane supported by four arms. The structure consists of a 0.6 μm-thick SiO₂ membrane of size 50 μm × 50 μm over which a platinum resistor is laid out. The simulation of the structure was carried out using MEMS-CAD Tool COVENTORWARE. The platinum resistor of 31.0 Ω is fabricated on SiO₂ membrane using lift-off technique. The bulk micromachining technique is used to create the suspended SiO₂ membrane. The temperature coefficient of resistance (TCR) of platinum used for temperature estimation of the hotplate is measured and found to be 2.2 × 10⁻³/°C. The test results indicate that the microhotplate consumes only 11.8 mW when heated up to 400 °C. For reliability testing, the hotplate is continuously operated at higher temperatures. It was found that at 404 °C, 508 °C and 595 °C, the microhotplate continuously operated up to 16.5 h, 4.3 h and 4 min respectively without degrading its performance. It can sustain at least 53 cycles pulse-mode of operation at 540 °C with ultra-low resistance and temperature drifts. The structure has maximum current capability of 19.06 mA and it can also sustain the ultrasonic vibration at least for 30 min without any damage.     

Material issues in electronic interconnects and packaging

Electronic packages consist of metallic, polymeric, and sometimes ceramic materials as integral entities. Individual physical and mechanical properties of these constituents, and their influence on each other's behavior, affect the overall reliability of the electronic packages. The most common failures in electronic interconnects arise from thermomechanical fatigue of the solder joints. Mismatches in coefficient of thermal expansion (CTE) that exist between these constituent materials are the main cause of such failures. Several approaches such as alloying and composite methodology are being explored to improve the reliability of the solder, which is metallic in nature, by improving its mechanical attributes. Other avenues such as matching the CTE of the constitutent materials are also being considered. In addition, the metallization of the electrical components and electrically non-conducting polymeric/ceramic layer to make it solderable has also been a source of concern regarding the joint reliability. Another concern relates to the high CTE of polymeric boards. This can cause significant CTE mismatch problems if silicon chips are directly mounted on them. Some of our significant findings in these respects are presented.     

Mechanical and electrical characterisation of Au wire interconnects in electronic packages under the combined vibration and thermal testing conditions

This paper concerns the reliability of thermosonically bonded 25 μm Au wires in the combined high temperature with vibration conditions, under which the tests have been carried out on wire-bonded 48-pin Dual-in-Line (DIL) High Temperature Co-fired Ceramic (HTCC) electronic packages. Mechanical, optical and electrical analysis has been undertaken in order to identify the failure mechanisms of bonded wires due to the combined testing. The results indicated a decrease in the electrical resistance after a few hours of testing as a result of the annealing process of the Au wire during testing. In general, ball shear and wire pull strength levels remained high after testing, showing no significant deterioration due to the tests under the combined high temperature and vibration conditions. However, a trend of the variation in the strength values is identified with respect to the combined conditions for all wire-bonded packages, which may be summarised as: (i) increase of the testing temperature has led to a decrease of both the shear and pull strength of the wire bonds; (ii) the mechanical behaviour of the wires is affected due to crystallisation that leads to material softening and consequently the deformation of wire.     

高科技制造工厂供配电系统探讨

阐述了高科技制造工厂对于电力的可靠性、稳定性、连续性的需求,从集成电路工厂供配电系统的特点和对供配电系统要求方面,进行了系统的说明和探讨。     

Delay and crosstalk reliability issues in mixed MWCNT bundle interconnects

Multi-walled carbon nanotube (MWCNT) bundles have potentially provided attractive solution in nanoscale VLSI interconnects. In current fabrication process, it is not trivial to grow a densely packed bundle having MWCNTs with similar number of shells. A realistic nanotube bundle, in fact, is a mixed CNT bundle consisting of MWCNTs of different diameters. This research paper presents an analytical model of mixed CNT bundle wherein MWCNTs having different number of shells are densely packed. Two different types of MWCNT bundles are presented: (1) MB that contains MWCNTs with similar number of shells (i.e., uniform diameters) and (2) MMB wherein MWCNTs having different number of shells (i.e., non-uniform diameters) are mixed. Multi-conductor transmission line theory is used to present an equivalent single-conductor (ESC) model of different MB and MMB configurations. Using the ESC model, performance is analyzed to address the effect of propagation delay, crosstalk and power dissipation that explores the reliability of an interconnect wire. It is observed that using an MMB arrangement, the overall reduction in delay and crosstalk are 15.33% and 29.59%, respectively, compared to the MB for almost similar power dissipation.     

薄金板可靠性研究及金厚控制

针对沉金工艺的PCB板,研究了板面金厚分布的规律,.时研究了金厚0.03μm产品的可靠性,进而对金厚的0.03μm板的金厚通过统计控制方法计算设定控制限进行控制,已达到成本控制的目的.     

大型环境试验设备中PLC控制系统的供电与接地

针对大型环境试验设备中的PLC控制系统从供电与接地方面分析了干扰对PLC控制器的影响和破坏，提出了一些提高PLC控制系统的可靠性的措施，以满足工业控制要求。     

对有核与无核多层基板的供电网络分析

由于具有高密度布线能力和相对合理的成本,在特殊用途集成电路(ASI Cs)的倒装封装中使用叠积层式(bui l d-up)有机基板非常受欢迎。典型的叠积层式基板包括核层和其双侧的高密度布线层(叠积层)。核层为封装提供所需刚度,其厚度可以是400μm,600μm,或800μm。新兴的无核基板技术去除了核层,可以提高布线密度,减薄封装,和获得更好的电气性能。本文比较了8层有核与无核基板在31mm和900锡球封装中的核心供电网络(PDN)的性能。在50MHz到2GHz频域内,我们用矢量网络分析仪测得两路高频S参数以分析相应的PDN。测量与模拟结果十分吻合。另外,我们还在时域内模拟计算了PDN对瞬变电流的响应。     

MPCVD金刚石膜沉积技术及金刚石膜材料在微波电真空器件中的应用

金刚石膜是一种集众多优异性能于一身的新材料,尤其是其热导率高、绝缘性能好以及微波介电损耗低等特点,使金刚石膜在微波电真空器件领域有着重要的应用前景。目前,以微波等离子体化学气相沉积（MPCVD）方法制备高品质金刚石膜的技术已趋向成熟。本文将针对微波电真空器件这一应用背景,简要介绍国内外高品质金刚石膜MPCVD沉积技术的发展现状,进而对金刚石膜材料应用于微波电真空器件领域的一些典型实例进行简单的介绍。     

强微波场中功率分布的采集与处理

该文提出一种测量微波场功率分布的有效方法.为了定量测量强微波场功率分布,设计了测试容器及多路温度同步采集和处理系统;并构造了两种算法对采样数据进行修正处理,给出了微波场功率分布的实验结果.此方法可行、可靠,很有实用价值.