多波长抽运C+L波段喇曼放大器的数值模拟与分析

为了合理地设计出宽带分布式光纤喇曼放大器系统,采用理论分析与数值模拟相结合的方法,对前向抽运方式的喇曼耦合方程进行数值仿真,获得了合适的抽运源波长,从而实现了分布式喇曼光纤放大器的带宽为80nm(1530nm～1610nm).在抽运功率均匀分配的情况下,对80个信道的信号进行分布式放大,分析了不同信号、抽运功率沿光纤的...     

A 105-nm ultrawide-band gain-flattened amplifier combining C- and L-band dual-core EDFAs in a parallel configuration

A novel structure for ultrawide-band gain-flattened amplifier by combining two pieces of C- and L-band dual-core erbium-doped fibers is reported. This novel amplifier has a flat gain of 15 dB over a wavelength range of 105 nm (1515-1620 nm). The gain variation for the C-band flat gain region (1515-1555 nm) is 1.3 dB, and for the L-band flat gain region (1562-1620 nm) is 1.5 dB. The noise figure varies from 4.5 to 4.8 dB over the whole bandwidth. The structure of the design is simple without the need of additional expensive components.     

240-km CWDM transmission using cascaded SOA Raman hybrid amplifiers with 70-nm bandwidth

We demonstrate the cascading of broad-band semiconductor optical amplifier-Raman hybrid amplifiers which provide nearly flat gain over 70 nm. A coarse-wavelength-division-multiplexing transmission system consisting of three spans of 80 km shows uniform performance and <1-dB power penalty.     

S+C bands amplification in a distributed Er-doped Raman fiber

A novel hybrid optical amplifier covering entire S- and C-bands has been proposed. A silica fiber configured with an erbium (Er)-doped cladding and a germanium-doped core was used. Amplification was achieved by stimulated Raman scattering along with the Er ions' radiative transition in a fiber. A numerical simulation has been performed to analyze the amplification characteristics. Fiber parameters such as optical loss, Er concentration, fiber length, and pump power were taken into consideration to calculate the optimum pump power and fiber length for a flat gain characteristic over the entire S- and C-bands.     

高性能低成本的C+L波段掺铒光纤光源

为了得到一种高性能的C+L波段的宽带掺铒光纤光源,用一个980nm和一个1480nm激光二极管作为抽运源,用两个3dB宽带耦合器作为光纤反射镜,同时利用功率控制电路让光源输出光稳定,对设计的光源进行了实验和理论验证,获得了功率为168.67mW(22.27dBm)、带宽达到80.701nm(1525.112nm～1605.813nm)的C+L波段宽带光源。结果表明,开始用两个980nm和一个1480nm二极管作为抽运源,之后改为一个980nm和一个1480nm二极管作为抽运源,并没有减少光源的输出功率,也没有改变稳定性。这一结果对减少光源的成本、提高光光转换效率,具有实际价值。     

A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation

A dual-path amplifier topology with dual-loop parallel compensation technique is proposed for low-power three-stage amplifiers. By using two parallel high-speed paths for high-frequency signal propagation, there is no passive capacitive feedback network loaded at the amplifier output. Both the bandwidth and slew rate are thus significantly improved. Implemented in a 0.6-/spl mu/m CMOS process, the proposed three-stage amplifier has over 100-dB gain, 7-MHz gain-bandwidth product, and 3.3-V//spl mu/s average slew rate while only dissipating 330 /spl mu/W at 1.5 V, when driving a 25-k/spl Omega///120-pF load. The proposed amplifier achieves at least two times improvement in bandwidth-to-power and slew-rate-to-power efficiencies than all other reported multistage amplifiers using different compensation topologies.     

C + L-band hybrid amplifier using FBGs for dispersion compensation and power equalisation

A serial type, C+L-band hybrid amplifier based on a single pump laser diode is proposed. Dispersion management and gain equalisation among C+L-band channels are realised simultaneously. Pump reflectors and double-pass schemes are used to increase the pump slope efficiency. The power variation is reduced from 6.5 to 0.2 dB among C + L band channels.     

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each other's phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.     

L.S.A. microstrip phase-locked power amplifier

A distributed amplifier structure is described using the l.s.a. mode of operation in a microstrip transmission line where gallium arsenide replaces the dielectric. The amplifier gain against frequency is given, and various practical design criteria are discussed.     

S+C+L超宽带光源的研究

为了得到一种高性能的S+C+L波段的超带宽光纤光源,采用一种新型的混合掺杂的光纤作为传输媒质,通过用激光二极管作为抽运源抽运掺铒光纤和掺铥光纤,用两个3dB宽带耦合器作为光纤反射镜,同时利用功率控制电路让光源输出光稳定,对设计的光源进行了实验和理论验证,得到了总功率为28mW、带宽1460nm～1610nm的S+C+L波段的超带宽光纤光源。结果表明,光纤环形镜的使用,不仅改善了光源的平坦度,并且大大提高了光光转换效率。     

A wide-band operational amplifier with a new output stage and a simple frequency compensation

Innovations in circuit design have resulted in a high-performance wide band operational amplifier made by standard integrated-circuit production processes. A new class-B output circuit with very low distortion and high quiescent current stability a coupling method for differential amplifier stages incorporating the elimination of amplifier stages at high frequencies to obtain a first-order frequency response and an input stage combined with a level shift with lateral p-n-p transistors having capacitive feed forward to increase the bandwidth are used in this amplifier. A unity gain bandwidth of 50 MHz with an open-loop voltage gain of 3.10/SUP 5/ and an input bias current of 10 nA are obtained.     

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET

Double-gate (DG) transistor has emerged as one of the most promising devices for nano-scale circuit design. In this paper, we propose a high-performance and robust sense-amplifier design using independent gate control in symmetric and asymmetric DG devices for sub-50-nm technologies. The proposed sense amplifier has better performance (30%-35% less sensing delay) and robustness (60%-80% less minimum input bit-differential for correct operation considering 10% worst case silicon thickness mismatch) compared to the connected gate design. Hence, the proposed design successfully demonstrates the benefit of using independent gate control in DG devices for efficient circuit design in sub-50-nm regime.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

A direct-coupled hybrid IC amplifier with 1-ns rise time

This paper describes the design and operation of a wide-band direct-coupled pulse amplifier, with a voltage gain of 10 and a rise time of 1 ns. Computer-aided analysis and simulation are used to optimize the design and to predict the performance of the amplifier. Good agreement is obtained between the predicted and experimental results. In an attempt to improve the frequency response through the reduction of parasitic capacitive and inductive effects, the amplifier has been fabricated as a hybrid IC by use of thin-film resistors and silicon chip transistors mounted on a ceramic substrate.     

一种新型带宽自动校准有源低通滤波器

为了消除工艺、电压、温度(Process,Voltage,Temperature,PVT)波动及老化对片上集成有源滤波器带宽的影响,提出了一种新型带宽自动校准有源低通滤波器.通过时域采样有源低通滤波器对输入的响应,并与参考电压进行比较,算法电路根据比较结果调整滤波器电容大小,自动搜索到最佳的滤波器带宽.为了消除带宽校准过程中电路响应延迟对校准精度的影响,在时钟及其二分频信号控制下分别执行一次校准,然后通过倍乘和减法运算得到最终对P VT波动、老化及电路响应延迟均不敏感的精确的滤波器带宽.在65 nm互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺下设计了一款带宽自动校准有源低通滤波器,仿真结果显示其低频增益为67 dB,在8～50 MHz带宽范围内带宽校准误差在0.7％以内.     

A novel fully differential biopotential amplifier with dc suppression

Fully differential amplifiers yield large differential gains and also high common mode rejection ratio (CMRR), provided they do not include any unmatched grounded component. In biopotential measurements, however, the admissible gain of amplification stages located before dc suppression is usually limited by electrode offset voltage, which can saturate amplifier outputs. The standard solution is to first convert the differential input voltage to a single-ended voltage and then implement any other required functions, such as dc suppression and dc level restoring. This approach, however, yields a limited CMRR and may result in a relatively large equivalent input noise. This paper describes a novel fully differential biopotential amplifier based on a fully differential dc-suppression circuit that does not rely on any matched passive components, yet provides large CMRR and fast recovery from dc level transients. The proposed solution is particularly convenient for low supply voltage systems. An example implementation, based on standard low-power op amps and a single 5-V power supply, accepts input offset voltages up to +/-500 mV, yields a CMRR of 102 dB at 50 Hz, and provides, in accordance with the AAMI EC38 standard, a reset behavior for recovering from overloads or artifacts.     

A CMOS power amplifier with a novel output structure

A two-stage op-amp with a novel output driver achieves 5.8-MHz GBW, 68° phase margin, and delivers 2.6 V_pp with a THD of 0.14% and 3.2 V_pp with a THD of 0.38% into 100 Ω at 20 kHz for a ±2.5-V supply. The output driver enables a very simple circuit measuring only 0.11 mm²     

A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops

A technique for bandwidth extension and noise optimization of wideband low-noise amplifier with dual feedback loops is presented. A LC-ladder matching network has been added in front of conventional amplifier with dual feedback loops. Detailed circuit analysis and general design procedures for the modified amplifier have been provided. The technique is applied to an amplifier covering the frequency range from DC to 6 GHz in a 0.5 μm InGaAs E-mode pHEMT process. Post-layout simulation shows S ₁₁ below ?10 dB, S ₂₂ below ?10 dB, flat S ₂₁ of 16 ± 0.2 dB, and flat NF of 1.85 ± 0.35 dB across the entire band, which confirms the improvement in bandwidth and noise performance.     

A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-/spl mu/m Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.