共查询到20条相似文献,搜索用时 15 毫秒
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提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试BIST(built-in self-test)设计方法,该方法在原始线性反馈移位寄存器LFSR(linear feedback shift register)的基础上加入若干逻辑,使测试向量每周期最多产生两次跳变,因而大大降低了被测电路CUT(circuit under test)的功耗。通过对组合电路集ISCAS’85的实验证明,被测电路的总功耗、平均功耗以及峰值功耗都有大幅度的降低。 相似文献
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一种新的低功耗BIST测试生成器设计 总被引:3,自引:1,他引:2
文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的BIST测试生成器设计方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑电路,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低.由于该设计方案比其它LPTPG方案的面积开销小,从而具有更好的使用价值. 相似文献
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针对组合电路内建自测试过程中的功耗和故障覆盖率等问题,提出了一种能获得较高故障覆盖率的低功耗测试矢量生成方案。该方案先借助A talanta测试矢量生成工具,针对不同的被测电路生成故障覆盖率较高的测试矢量,再利用插入单跳变测试矢量的方法以及可配置线性反馈移位寄存器生成确定性测试向量的原理,获得低功耗测试矢量。通过对组合电路集ISCAS’85的实验,证实了这种测试生成方案的有效性。 相似文献
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Nadir Z. Basturkmen Sudhakar M. Reddy Irith Pomeranz 《Journal of Electronic Testing》2003,19(6):637-644
Peak power consumption during testing is an important concern. For scan designs, a high level of switching activity is created in the circuit during scan shifts, which increases power consumption considerably. In this paper we propose a pseudo-random BIST scheme for scan designs, which reduces the peak power consumption as well as the average power consumption as measured by the switching activity in the circuit. The method reduces the switching activity in the scan chains and the activity in the circuit under test by limiting the scan shifts to a portion of the scan chain structure using scan chain disable. Experimental results on various benchmark circuits demonstrate that the technique reduces the switching activity caused by scan shifts. 相似文献
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Minimized Power Consumption for Scan-Based BIST 总被引:1,自引:1,他引:0
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture are analyzed, the modules and modes with the highest power consumption are identified, and design modifications to reduce power consumption are proposed. The design modifications include some gating logic for masking the scan path activity during shifting, and the synthesis of additional logic for suppressing random patterns which do not contribute to increase the fault coverage. These design changes reduce power consumption during BIST by several orders of magnitude, at very low cost in terms of area and performance. 相似文献
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本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的. 相似文献
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针对扫描结构混合模式BIST的特点,文章提出了一种利用双模式LFSR和新型折叠控制器相结合的方法来对基于扫描结构的混合模式BIST电路进行低功耗优化设计,从而达到降低待测电路功耗的目的. 相似文献
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Jacob Savir 《Journal of Electronic Testing》2000,16(4):369-380
To successfully combat delay faults there is an urgent need for a proper design for testability (DFT). The foundation of any DFT methodology rests on its scan design. This paper describes three versions of a new design of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of this new SRL is faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Adoption of this new DFT methodology brings us closer to the ideal target of one test-per-clock as opposed to one test-per-scan. Operation, cost, and other attributes are studied in detail. Results of adopting one of these SRLs are reported on ten pilot chips. 相似文献
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文章介绍了一种功耗比标准蓝牙更低的超低功耗蓝牙技术,描述了这种技术的由来、协议栈构成、拓扑结构、Radio层的工作状态和工作角色以及特点。在技术特点部分中,详细介绍了超低功耗蓝牙技术实现低功耗的原理,并且给出了它与标准蓝牙技术的参数相对比的表格。 相似文献
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在无人机3D地形测绘中,作为核心模块的时间数字转换器(TDC)需要具有远距离测量能力和高测量分辨率。基于对测距系统的长续航、公里级测距能力和厘米级测量精度的综合考量,文章设计了一种用于TDC的低功耗多相位时钟生成电路。采用了伪差分环形压控振荡器,通过优化交叉耦合结构,在保证低功耗的前提下,提升了信号边缘的斜率,增强了时钟的抖动性能和对电源噪声的抑制能力。在电荷泵设计中,通过对环路带宽的考量选取了极低的偏置电流,在进一步降低功耗的同时缩小了环路滤波器的面积。基于SMIC 180 nm CMOS工艺完成了对多相时钟生成电路的设计。仿真结果表明,在400 MHz的输出频率下,环路带宽稳定在1 MHz。该电路在不同工艺角下均能达到较快的锁定速度,相位噪声为-88 dBc@1 MHz,功耗为1 mW,均方根抖动为27 ps,满足厘米级测距的精度需求。 相似文献
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基于SMIC 0.18μm CMOS工艺,设计了一种基于电容充放电的新型低功耗时钟发生器。为了减小温度变化引起的频率波动,设计了负温度系数偏置电路。采用了传统的占空比调节电路,可调节振荡波形的占空比。仿真结果显示,在3.3 V电源电压下,该振荡器可以稳定输出7.16 MHz频率的信号,相位噪声为-104.4 dBc/Hz,系统功耗为1.411 mW,其中环形振荡器功耗为0.811 mW。在-40℃~110℃温度变化范围内,振荡器的频率变化为7.116~7.191 MHz,容差在1.05%以内。同其他时钟发生器相比,该电路具有结构简单、功耗低,以及在宽温度范围内具有较高的频率稳定性等显著特点,能够满足芯片的工作要求,为芯片提供稳定时钟。 相似文献