阶梯氧化层新型折叠硅横向双扩散功率器件

为了设计功率集成电路所需的低功耗横向功率器件, 提出了一种具有阶梯氧化层折叠硅横向双扩散金属-氧化物-半导体(step oxide folding LDMOS, SOFLDMOS)新结构. 这种结构将阶梯氧化层覆盖在具有周期分布的折叠硅表面, 利用阶梯氧化层的电场调制效应, 通过在表面电场分布中引入新的电场峰而使表面电场分布均匀, 提高了器件的耐压范围, 解决了文献提出的折叠积累型横向双扩散金属-氧化物-半导体器件击穿电压受限的问题. 通过三维仿真软件ISE分析获得, SOFLDMOS 结构打破了硅的极限关系, 充分利用了电场调制效应、多数载流子积累和硅表面导电区倍增效应, 漏极饱和电流比一般LDMOS 提高3.4倍左右, 可以在62 V左右的反向击穿电压条件下, 获得0.74 mΩ·cm²超低的比导通电阻, 远低于传统LDMOS相同击穿电压下2.0 mΩ·cm²比导通电阻, 为实现低压功率集成电路对低功耗横向功率器件的要求提供了一种可选的方案.     

分离作用RFQ膜片电极的优化设计

用RELAX3D模拟分离作用射频四极场(SFRFQ)加速结构中傍轴下的电场分布，并分析了膜片孔径、加速间隙等参数对粒子能量增益的影响，找到了设计SFRFQ电极的一般方法，使得在极间电压为70kV的情况下(以O⁺为例)，粒子通过一个周期单元，可获得100keV以上的能量增益，小球微扰法的测量值与模拟结果能很好的符合. 关键词： 分离作用射频四极场 RELAX3D 能量增益 反场     

电荷非平衡super junction结构电场分布

建立了电荷非平衡情况下super junction(SJ)耐压结构的二维电场分布理论模型. 获得了浓度和宽度非平衡、梯形n-/p- 区和横向线性缓变掺杂三种非平衡SJ结构的电场分布. 理论分析结果与二维器件数值仿真软件MEDICI的仿真结果符合良好. 虽然给出的电场分布为三角级数形式, 但仍能从中获得很多重要信息. 特别地, 由此可求出非平衡SJ结构的峰值电场和耐压. 该结果有助于对SJ结构的深入分析. 关键词： super junction 电场分布 电荷非平衡     

Reverse blocking characteristics and mechanisms in Schottky-drain AlGaN/GaN HEMT with a drain field plate and floating field plates

In this paper, a novel Al Ga N/Ga N HEMT with a Schottky drain and a compound field plate(SD-CFP HEMT) is presented for the purpose of better reverse blocking capability. The compound field plate(CFP) consists of a drain field plate(DFP) and several floating field plates(FFPs). The physical mechanisms of the CFP to improve the reverse breakdown voltage and to modulate the distributions of channel electric field and potential are investigated by two-dimensional numerical simulations with Silvaco-ATLAS. Compared with the HEMT with a Schottky drain(SD HEMT) and the HEMT with a Schottky drain and a DFP(SD-FP HEMT), the superiorities of SD-CFP HEMT lie in the continuous improvement of the reverse breakdown voltage by increasing the number of FFPs and in the same fabrication procedure as the SD-FP HEMT.Two useful optimization laws for the SD-CFP HEMTs are found and extracted from simulation results. The relationship between the number of the FFPs and the reverse breakdown voltage as well as the FP efficiency in SD-CFP HEMTs are discussed. The results in this paper demonstrate a great potential of CFP for enhancing the reverse blocking ability in Al Ga N/Ga N HEMT and may be of great value and significance in the design and actual manufacture of SD-CFP HEMTs.     

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper for the first time, a partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) is proposed with a novel trench which improves breakdown voltage. The introduced trench in the partial buried oxide enhances peak of the electric field and is positioned in the drain side of the drift region to maximize breakdown voltage. We demonstrate that the electric field is modified by producing two additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the trench-partial-silicon-on-insulator (T-PSOI) structure. Hence, a more uniform electric field is obtained. Two dimensional (2D) simulations show that the breakdown voltage of T-PSOI is nearly 64% higher in comparison with partial silicon on insulator (PSOI) structure and alleviate self heating effect approximately 9% and 15% in comparison with its conventional PSOI (C-PSOI) and conventional SOI (C-SOI) counterparts respectively. In addition the current of the T-PSOI, C-PSOI, conventional SOI (C-SOI), and fully depleted conventional SOI (FC-SOI) structures are 90, 82, 74, and 44 μA, respectively for a drain–source voltage V_DS = 30 V and gate–source voltage V_GS = 10 V.     

Analysis of the modulation mechanisms of the electric field and breakdown performance in AlGaN/GaN HEMT with a T-shaped field-plate

A novel Al Ga N/Ga N high electron mobility transistor(HEMT) with a source-connected T-shaped field-plate(ST-FP HEMT) is proposed for the first time in this paper. The source-connected T-shaped field-plate(ST-FP) is composed of a source-connected field-plate(S-FP) and a trench metal. The physical intrinsic mechanisms of the ST-FP to improve the breakdown voltage and the FP efficiency and to modulate the distributions of channel electric field and potential are studied in detail by means of two-dimensional numerical simulations with Silvaco-ATLAS. A comparison to the HEMT and the HEMT with an S-FP(S-FP HEMT) shows that the ST-FP HEMT could achieve a broader and more uniform channel electric field distribution with the help of a trench metal, which could increase the breakdown voltage and the FP efficiency remarkably. In addition, the relationship between the structure of the ST-FP, the channel electric field, the breakdown voltage as well as the FP efficiency in ST-FP HEMT is analyzed. These results could open up a new effective method to fabricate high voltage power devices for the power electronic applications.     

A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines

In this paper, a novel silicon on insulator (SOI) lateral diffused metal oxide semiconductor (LDMOS) transistor with high voltage and high frequency performance is presented. In this work we try to reduce the electric field crowding in the drift region. The proposed structure consists of a metal in the buried oxide and also connected to the source. The inserted metal attracts the electric field lines in the buried oxide. It causes 67% improvement in the breakdown voltage in comparison with a conventional SOI-LDMOS (C-LDMOS). Our simulations with two dimensional ATLAS simulator show that the gate-drain capacitance improves in the proposed structure. The unilateral power gain also enhances. So, the proposed structure is suitable for high voltage and high frequency applications.     

基于对称广义Fibonacci光子晶体结构的电光可调谐滤波器

本文构建了含有电光材料LiNbO₃的一维对称广义Fibonacci光子晶体结构,提出并设计了一种基于该结构的可调谐滤波器,并利用传输矩阵法对设计的滤波器的可调谐滤波特性进行了理论研究.数据模拟结果表明:保持对称广义Fibonacci光子晶体的几何结构不变,通过改变电极所在处施加在电光介质(LiNbO₃)层上的外加电场,即可实现滤波器的滤波通道波长的调节,滤波通道波长的改变与外加电压呈线性关系,随着外加电压的增加,滤波通道波长向短波长方向移动.此外,电压一定时,通道波长随光的入射角的增加向短波长方向移动;光的入射角一定时,外加正电压下,通道波长随电压增加发生蓝移,而外加负电压下,通道波长随反向电压的增加发生红移.最后,讨论了双电场作用下的多通道波长滤波器的结构极其特性.以上结果对于新型光子晶体器件的设计具有重要的参考价值.     

基于对称广义Fibonacci光子晶体结构的电光可调谐滤波器

本文构建了含有电光材料LiNbO3的一维对称广义Fibonacci光子晶体结构,提出并设计了一种基于该结构的可调谐滤波器,并利用传输矩阵法对设计的滤波器的可调谐滤波特性进行了理论研究.数据模拟结果表明:保持对称广义Fibonacci光子晶体的几何结构不变,通过改变电极所在处施加在电光介质(LiNbO3)层上的外加电场,...     

Design and performance considerations of novel 4H–SiC MESFET with a p-type pillar for increasing breakdown voltage

In this paper, we report a novel Super Junction Metal Semiconductor Field Effect Transistor (SJ-MESFET) where the drift region consists of a p-type pillar in order to improve breakdown voltage. We demonstrate that the depletion region in the drift region can be extended entirely by the p-type pillar leading to a uniform electric field. Therefore breakdown voltage significantly improves. Using two-dimensional and two-carrier device simulation, we have analyzed the various performance and design considerations of the SJ-MESFET. Also we have explained the reasons for improving the performance of the SJ-MESFET when compared to a Conventional Bulk MESFET (CB-MESFET). Detailed numerical simulations demonstrate that for the proposed structure due to decrease in parasitic gate-to-drain capacitor, maximum oscillation frequency increases with respect to CB-MESFET.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

纳秒脉冲下高气压SF6中同轴绝缘子沿面闪络影响因素实验研究

研究纳秒脉冲下的绝缘子沿面闪络影响因素对电磁脉冲模拟装置绝缘结构设计具有重要的借鉴意义。通过搭建绝缘子沿面闪络实验平台,实验研究了在0.5 MPa的SF6气体中,脉冲电压波形、绝缘材料和绝缘子沿面场强分布对绝缘子沿面闪络电压的影响。结果表明：绝缘子的闪络电压具有随着脉冲前沿时间减小而增加的趋势;相较于脉冲电压全波,绝缘子在脉冲电压前沿波形耐受下闪络电压较高;聚酰亚胺材料的绝缘性能最好;通过降低绝缘子沿面最大场强,改善电场分布可以有效地提高绝缘子的闪络电压。     

Influence of the corona-wire diameter and length on corona discharge characteristics of a cylindrical tri-axial charger

In this paper, the corona discharge characterization in terms of current–voltage relationships of a unipolar cylindrical tri-axial charger on the effects of the corona wire diameter and length have been experimentally studied and discussed. A commercial computational fluid dynamics software package, COMSOL Multiphysics™, was used to predict the electric field distribution in the ion generation and charging zones of the charger and the ion penetration through the perforated screen opening on the inner electrode of the charger. It was found from experimental results that both positive and negative charging currents in the charging zone of the charger increased with increasing corona and ion-driving voltages. At the same corona and ion-driving voltages, both positive and negative coronas were decreased with increasing diameter of the corona-wire. Compared with the corona-wire of 22 mm in length, the magnitude of both positive and negative charging currents were markedly higher for corona-wire of 11 mm in length at the same corona voltage. It was found that the charging currents for negative coronas were about 1.2 times higher than those positive coronas at the same corona and ion-driving voltages. Numerical results of the electric field distribution and the ion and charged particles migrations in the discharge and charging zones of the charger is correlated to have the same direction with the experimental results of the current–voltage relationships. Also, this can be used to guidance in describing the electric field distribution and the behavior of ion and charged particle trajectories that cannot be seen from experiments in order to improve the applicably design and refinement of a unipolar cylindrical tri-axial charger.     

新型高速半导体器件IMOS阈值电压解析模型

本文在研究IMOS器件结构的基础上, 分析了该器件不同区域的表面电场, 结合雪崩击穿条件, 建立了P-IMOS的阈值电压解析模型. 应用MATLAB对该器件阈值电压模型与源漏电压、栅长和硅层厚度的关系进行了数值分析, 并用二维器件仿真工具ISE进行了验证. 结果表明, 源电压越大, 阈值电压值越小; 栅长所占比例越大, 阈值电压值越小, 硅层厚度越小, 阈值电压值越小. 本文提出的模型与ISE仿真结果一致, 也与文献报道符合. 这种新型高速半导体器件IMOS阈值电压解析模型的建立为该高性能器件及对应电路的设计、仿真和制造提供了重要的参考.     

背栅效应对SOI横向高压器件击穿特性的影响

提出一种SOI基背栅体内场降低BG REBULF(back-gate reduced BULk field)耐压技术. 其机理是背栅电压诱生界面电荷，调制有源区电场分布，降低体内漏端电场，提高体内源端电场，从而突破习用结构的纵向耐压限制，提高器件的击穿电压. 借助二维数值仿真，分析背栅效应对厚膜高压SOI LDMOS (>600V) 击穿特性的影响，在背栅电压为330V时，实现器件击穿电压1020V，较习用结构提高47.83%. 该技术的提出，为600V以上级SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路. 关键词： SOI 背栅 体内场降低 LDMOS     

A Particle‐in‐Cell Simulation of the Breakdown Mechanism in Microdischarges with an Improved Secondary Emission Model

In this paper, the failure of the breakdown voltage from the Paschen's law at extremely small electrode separations is studied. The electrical breakdown in microgaps occurs at the voltages far below the Paschen curve minimum breakdown limit and the modified Paschen curve should be used. Offered explanation for the departure from the Paschen's law at small gap spacings is based on the increasing of the yield of the secondary electrons. The high electric fields existing in small gaps may enhance the secondary electron yield and this would lead to a lowering of the breakdown voltage and to the departure from the Paschen's law. Particlein‐cell/Monte‐Carlo (PIC/MCC) simulations with a new secondary emission model have been performed to estimate the importance of this mechanism in the discharge breakdown. Obtained simulation results suggest that deviations from the Paschen curve across the micron and submicorn gap spacing can be attributed to the ion‐enhanced field emissions. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

A new analytical model of high voltage silicon on insulator （SOI） thin film devices

A new analytical model of high voltage silicon on insulator (SOI) thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon film thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1μm which is much larger than the normal value of about 30V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage (V_B,V) are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.     

Two-dimensional threshold voltage model of nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor (TFET) is a potential candidate for the post-CMOS era. In this paper, a threshold voltage model is developed for this new kind of device. First, two-dimensional (2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions. Then based on the physical definition of threshold voltage for the nanoscale TFET, the threshold voltage model is developed. The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data. It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper. This threshold voltage model provides a valuable reference to the TFET device design, simulation, and fabrication.     

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.