Rapid thermal annealing induced changes on the contact of Ni/Au to N-doped ZnO

N-doped p-type ZnO (p ∼ 10¹⁸cm^-3) was grown on sapphire(0 0 0 1) substrate by metal-organic chemical vapor deposition method. Ni/Au metal was evaporated on the ZnO film to form contacts. As-deposited contacts were rectifying while ohmic behavior was achieved after thermally annealing the contacts in nitrogen environment. Specific contact resistance was determined by circular transmission line method and a minimum specific contact resistance of 8 × 10⁻⁴ Ω cm² was obtained for the sample annealed at 650 °C for 30 s. However, Hall effect measurements indicate that, as the rapid thermal annealing temperature increased up to 550 °C or higher the samples’ conductive type have changed from p-type to n-type, which may be due to the instability nature of the present-day p-type N-doped ZnO or the dissociation of ZnO caused by annealing process in N₂ ambient. Evolution of the sample's electric characteristics and the increment of metal/semiconductor interface states induced by rapid thermal annealing process are supposed to be responsible for the improvement of electrical properties of Au/Ni/ZnO.     

Theoretical investigations for zinc blende-wurtzite polytypism in GaAs layers at Au/GaAs(1 1 1) interfaces

The zinc blende (ZB)-wurtzite (W) polytypism of GaAs layers at the Au/GaAs(1 1 1)B interfaces is investigated based on total-energy electronic-structure calculations within density functional theory. The calculations for the abrupt interfaces including a GaAs top layer with ZB and W stacking sequences reveal that the ZB sequence is energetically favorable, but the energy of W sequence with an interstitial Au atom at the top GaAs layer of the interface is lower than that of ZB sequence. This is because electrons accumulate around the interstitial region due to the hybridization between Au-6s and As-4p orbitals, resulting in the reduction of Ga-As bond charges. As a result, the relative stability at the top GaAs layer is determined by the electrostatic energy due to ionic charges. The results imply that the stabilization of W sequence at the Au catalyst-semiconductor interfaces as well as that on the nanowire faces are the origins for the appearance of W segments in NWs, qualitatively consistent with experiments.     

Auger electron spectroscopy of Au/NiOx contacts on p-GaN annealed in N2 and O2 + N2 ambients

We have designed a promising contact scheme to p-GaN. Au/NiO_x layers with a low concentration of O in NiO_x are deposited on p-GaN by reactive dc magnetron sputtering and annealed in N₂ and in a mixture of O₂ + N₂ to produce low resistivity ohmic contacts. Annealing has been studied of NiO_x layers with various contents of oxygen upon the electrical properties of Au/NiO_x/p-GaN. It has been found that the Au/NiO_x/p-GaN structure with a low content of oxygen in NiO_x layer provides a low resistivity ohmic contact even after subsequent annealing in N₂ or O₂ + N₂ ambient at 500 °C for 2 min.Auger depth profiles and transmission electron microscopy (TEM) micrographs reveal that while annealing in O₂ + N₂ ambient results in reconstruction of the initial deposited Au/NiO_x/p-GaN contact structure into a Au/p-NiO/p-GaN structure, annealing in N₂ brings about reconstruction into Au/p-NiO/p-GaN and Ni/p-NiO/p-GaN structures. Hence, in both cases, after annealing in N₂ as well as in O₂ + N₂ ambient, the ohmic properties of the contacts are determined by creation of a thin oxide layer (p-NiO) on the metal/p-GaN interface. Higher contact resistivities in the samples annealed in O₂ + N₂ ambient are most likely caused by a smaller effective area of the contact due to creation of voids.     

Metal contacts to n-GaN

Al, Au, Ti/Al and Ti/Au contacts were prepared on n-GaN and annealed up to 900 °C. The structure, phase and morphology were studied by cross-sectional transmission and scanning electron microscopy as well as by X-ray diffraction (XRD), the electrical behaviour by current-voltage measurements. It was obtained that annealing resulted in interdiffusion, lateral diffusion along the surface, alloying and bowling up of the metal layers. The current-voltage characteristics of as-deposited Al and Ti/Al contacts were linear, while the Au and Ti/Au contacts exhibited rectifying behaviour. Except the Ti/Au contact which became linear, the contacts degraded during heat treatment at 900 °C. The surface of Au and Ti/Au contacts annealed at 900 °C have shown fractal-like structures revealed by scanning electron microscopy. Transmission electron microscopy and XRD investigations of the Ti/Au contact revealed that Au diffused into the n-GaN layer at 900 °C. X-ray diffraction examinations showed, that new Ti₂N, Au₂Ga and Ga₃Ti₂ interface phases formed in Ti/Au contact at 900 °C, new Ti₂N phase formed in Ti/Al contact at 700 and 900 °C, as well as new AlN interface phase developed in Ti/Al contact at 900 °C.     

Effect of surface preparation on the properties of Au/p-Cd1−xZnxTe

The effect of bromine methanol (BM) etching and NH₄F/H₂O₂ passivation on the Schottky barrier height between Au contact and semi-insulated (SI) p-Cd_1−xZn_xTe (x ≈ 0.09-0.18) was studied through current-voltage (I-V) and capacitance-voltage (C-V) measurements. Near-infrared (NIR) spectroscopy technique was utilized to determine the Zn concentration. X-ray photoelectron spectroscopy (XPS) for surface composition analysis showed that BM etched sample surface left a Te⁰-rich layer, however, which was oxidized to TeO₂ and the surface [Te]/([Cd] + [Zn]) ratio restored near-stoichiometry after NH₄F/H₂O₂ passivation. According to I-V measurement, barrier height was 0.80 ± 0.02-0.85 ± 0.02 eV for Au/p-Cd_1−xZn_xTe with BM etching, however, it increased to 0.89 ± 0.02-0.93 ± 0.02 eV with NH₄F/H₂O₂ passivation. Correspondingly, it was about 1.34 ± 0.02-1.43 ± 0.02 eV and 1.41 ± 0.02-1.51 ± 0.02 eV by C-V method.     

Inhomogeneities in 130 MeV Au ion irradiated Au/n-Si (1 0 0) Schottky structure

The electrical characteristics of Au/n-Si (1 0 0) Schottky rectifier have been studied in a wide irradiation fluence range using conventional current-voltage (I-V) and capacitance-voltage (C-V) measurements. The I-V characteristics showed an abnormal increase in forward current at low voltage. The device shows a bend in forward I-V and reverses bias C-V characteristics due to extra current, suggesting that there are two independent contributions to thermionic current, corresponding to two levels of the Schottky barrier. It is shown that the excess current at low voltage can be explained by taking into account the role of heavy ion irradiation induced defects at the metal semiconductor interface.     

Determination of the laterally homogeneous barrier height of thermally annealed and unannealed Au/p-InP/Zn-Au Schottky barrier diodes

We have identically prepared Au/p-InP Schottky barrier diodes (SBDs). The diodes were annealed up to 400 °C thermally. The barrier height (BH) for the as-deposited Au/p-InP/Zn-Au SBDs from the current-voltage characteristics have varied from 0.58 to 0.72 eV, and ideality factor n from 1.14 to 1.47. The BH for the annealed SBDs from the current-voltage characteristics have varied from 0.76 to 0.82 eV, and ideality factor n from 1.17 to 1.39. As a result of the thermal annealing, it has been seen that the BH values of the annealed SBDs are larger than those of the as-deposited SBDs. We have determined a lateral homogeneous BH value of 0.72 eV for the as-deposited Au/p-InP SBD from the experimental linear relationship between barrier heights and ideality factors, and a value of 0.85 eV for the annealed Au/p-InP SBD. The increase of 0.13 eV in the BH value by means of 400 °C annealing has been ascribed to the formation of the excess charges that electrically actives on the semiconductor surface.     

Electrical characteristics of polycrystalline Si layers embedded into high-k Al2O3 gate layers

The electrical characteristics of polycrystalline Si (poly Si) layers embedded into high-k Al₂O₃ (alumina) gate layers are investigated in this work. The capacitance versus voltage (C-V) curves obtained from the metal-alumina-polysilicon-alumina-silicon (MASAS) capacitors exhibit significant threshold voltage shifts, and the width of their hysteresis window is dependent on the range of the voltage sweep. The counterclockwise hysteresis observed in the C-V curves indicates that electrons originating from the p-type Si substrate in the inversion condition are trapped in the floating gate layer consisting of the poly Si layer present between the top and bottom Al₂O₃ layers in the MASAS capacitor. Also, current versus voltage (I-V) measurements are performed to examine the electrical characteristics of the fabricated capacitors. The I-V measurements reveal that our MASAS capacitors show a very low leakage current density, compared to the previously reported results.     

Formation of defect structures in Au-polysilane interfaces probed by low energy positron beams

Formation and accumulation of defect structures at interfaces between polysilanes and vacuum-evaporated gold (Au) electrodes are discussed quantitatively by low energy positron annihilation spectroscopy. The size distribution of the defects at the interface is analyzed based on the values of ortho-positronium (o-Ps) lifetime (τ₃), and no effect of the evaporation process is observed in the polymer films. The intensity of o-Ps (I₃) indicates no considerable change before and after Au evaporation on dialkyl-substituted polysilanes, however, the values of I₃ is increased ∼20% in phenyl-substituted polysilane (PMPS) by the evaporation. The I₃ dependence on incident positron energy suggests the formation of the defects not only at an Au-PMPS interface but also in PMPS bulk phase as deep as 400 nm from the interface. Phenyl ring dissociation from the polymer backbone will play a significant role in the selective formation of the defects in PMPS. This is the first report on the direct measurement of defect structures at conjugated polymer-metal interface with non-destructive way, implying that electrode fabrication by vacuum evaporation affects the solid state structure of polymers.     

Current-voltage characteristics of Au/GaN/GaAs structure

Au/GaN/n-GaAs structure has been fabricated by the electrochemically anodic nitridation method for providing an evidence of achievement of stable electronic passivation of n-doped GaAs surface. The change of the electronic properties of the GaAs surface induced by the nitridation process has been studied by means of current-voltage (I-V) characterizations on Schottky barrier diodes (SBDs) shaped on gallium nitride/gallium arsenide structure. Au/GaN/n-GaAs Schottky diode that showed rectifying behavior with an ideality factor value of 2.06 and barrier height value of 0.73 eV obeys a metal-interfacial layer-semiconductor (MIS) configuration rather than an ideal Schottky diode due to the existence of GaN at the Au/GaAs interfacial layer. The formation of the GaN interfacial layer for the stable passivation of gallium arsenide surface is investigated through calculation of the interface state density N_ss with and without taking into account the series resistance R_s. While the interface state density calculated without taking into account R_s has increased exponentially with bias from 2.2×10¹² cm⁻² eV⁻¹ in (E_c−0.48) eV to 3.85×10¹² cm⁻² eV⁻¹ in (E_c−0.32) eV of n-GaAs, the N_ss obtained taking into account the series resistance has remained constant with a value of 2.2×10¹² cm⁻² eV⁻¹ in the same interval. This has been attributed to the passivation of the n-doped GaAs surface with the formation of the GaN interfacial layer.     

Temperature-dependent optical absorption measurements and Schottky contact behavior in layered semiconductor n-type InSe(:Sn)

The layered n-InSe(:Sn) single crystal samples have been cleaved from a large crystal ingot grown from non-stoichiometric melt by the Bridgman-Stockbarger method. It has been made the absorption measurements of these samples without Schottky contact under electric fields of 0.0 and 6000 V cm⁻¹. The band gap energy value of the InSe:Sn has been calculated as 1.36 ± 0.01 eV (at 10 K) and 1.28 ± 0.01 eV (at 300 K) under zero electrical field, and 1.31 ± 0.01 eV (at 10 K) and 1.26 ± 0.01 eV (at 300 K) under 6000 Vcm⁻¹. The current-voltage (I-V) characteristics of Au-Ge/InSe(:Sn)/In Schottky diodes have been measured in the temperature range 80-320 K with a temperature step of 20 K. An experimental barrier height (BH) Φ_ap value of about 0.70 ± 0.01 eV was obtained for the Au-Ge/InSe(:Sn)/In Schottky diode at the room temperature (300 K). An abnormal decrease in the experimental BH Φ_b and an increase in the ideality factor n with a decrease in temperature have been explained by the barrier inhomogeneities at the metal-semiconductor interface. From the temperature-dependent I-V characteristics of the Au-Ge/InSe(:Sn)/In contact, that is, and A^* as 0.94 ± 0.02 and 0.58 ± 0.02 eV, and 27 ± 2 and 21 ± 1 (A/cm² K²), respectively, have been calculated from a modified versus 1/T plot for the two temperature regions. The Richardson constant values are about two times larger than the known value of 14.4 (A/cm² K²) known for n-type InSe. Moreover, in the temperature range 80-320 K, we have also discussed whether or not the current through the junction has been connected with TFE.     

Investigation on the barrier height and inhomogeneity of nickel silicide Schottky

The apparent Schottky barrier height (SBH) of the nickel silicide Schottky contacts annealed at different temperatures was investigated based on temperature dependence of I-V characteristic. Thermionic emission-diffusion (TED) theory, single Gaussian and double Gaussian models were employed to fit I-V experimental data. It is found the single Gaussian and double Gaussian SB distribution model can give a very good fit to the I-V characteristic of apparent SBH for different annealing temperatures. Also, the apparent SBH and the leakage current increase with annealing temperatures under reverse voltage. In addition, the homogeneity of interfaces for the samples annealed at temperatures of 500 and 600 °C is much better than that of the samples annealed at temperatures of 400, 700, and 800 °C. This may result from the phase transformation of nickel silicide due to the different annealing temperatures and from the low Schottky barrier (SB) patches.     

PdSi based ohmic contact on n-InP

The electrical and microstructural properties of the PdSi based ohmic contacts on n-InP are discussed in the research. A low specific contact resistance of 2.25 × 10⁻⁶ Ω cm² is obtained on Au/Si/Pd/n-InP contact after rapid thermal annealing (RTA) at 450 °C for 30 s. The low contact resistance can be maintained at the order of 10⁻⁶ Ω cm² even up to 500 °C annealing. From the Auger analysis, it is found that both the outdiffusion of In and the indiffusion of Si into the InP surface occurred at the ohmic contact sample. The formation of the Pd₃Si compound lowered the barrier of the contact. The reactions between Pd and InP of the contact, forming In vacancies, and leading the doping of Si to the InP contact interface.     

High reflective p-GaN/Ni/Ag/Ti/Au Ohmic contacts for flip-chip light-emitting diode (FCLED) applications

The fabrication of high reflective Ni/Ag/(Ti, Mo)/Au Ohmic contacts for flip-chip light-emitting diode (FCLED) are proposed and considered, Ni/Ag/Au Ohmic contacts are also fabricated to compare their resulting reflectivities. From secondary ion mass spectrometry (SIMS) depth profiles, it indicates that the Au in-diffusion occurs in Ni/Ag/Au contacts after annealing. It is considered that Au in-diffusion, which is intermixed with Ag, Ni and GaN in Ni/Ag/Au contacts after annealing, is responsible for the resulting low reflectance (63% at the wavelength of 465 nm). To avoid Au in-diffusion and enhance the reflectivity, a diffusion barrier metal (Ti or Mo) between Ni/Ag and Au is fabricated and examined. It is demonstrated and found that an insertion of diffusion barrier metal of Ti enables to block Au diffusion effectively and also improve the reflectivity significantly, up to 93%.     

An electrostatic force microscope study of Si nanostructures on Si(1 0 0) as a function of post-annealing temperature and time

The evolution of Si nanostructures induced by Ar⁺ ion sputtering on Si(1 0 0) was studied with electrostatic force microscopy (EFM) as a function of post-annealing temperature (T = room temperature-800 °C) and time (t = 0-160 min). The post-annealing of the nanostructure was conducted in vacuum. It was found that with T increasing, the EFM contrast degraded steadily and became nearly undetectable at T = 800 °C; with t increasing at T = 800 °C, the EFM contrast fell down steadily as well. However, the surface morphology and roughness were much less affected after annealing. The results suggest that the as-formed Si nanostructures may not be epitaxially grown on Si(1 0 0) substrate as claimed before. A plane capacitance model supported this conclusion.     

Ta/Ni/Ta multilayered ohmic contacts on n-type SiC

The interface formation, electrical properties and the surface morphology of multilayered Ta/Ni/Ta/SiC contacts were reported in this study. It was found that the conducting behavior of the contacts so fabricated is much dependent on the metal layer thickness and the subsequent annealing temperature. Auger electron spectroscopy (AES) and X-ray diffraction analyses revealed that Ni₂Si and TaC formed as a result of the annealing. The Ni atoms diffused downward to metal/SiC interface and converted into Ni₂Si layer in adjacent to the SiC substrate. The released carbon atoms reacted with Ta atoms to form TaC layer. Ohmic contacts with specific contact resistivity as low as 3 × 10⁻⁴ Ω cm² have been achieved after thermal annealing. The formation of carbon vacancies at the Ni₂Si/SiC interface, probably created by dissociation of SiC and formation of TaC during thermal annealing, should be responsible for the ohmic formation of the annealed Ta/Ni/Ta contacts. The addition of Ta into the Ni metallization scheme to n-SiC restricted the accumulation of carbon atoms left behind during Ni₂Si formation, improving the electrical and microstructure properties.     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

Influence of surface cleaning effects on properties of Schottky diodes on 4H-SiC

Ir/4H-SiC and IrO₂/4H-SiC Schottky diodes are reported in terms of different methods of surface pretreatment before contact deposition. In order to find the effect of surface preparation processes on Schottky characteristics the SiC wafers were respectively cleaned using the following processes: (1) RCA method followed by buffered HF dip. Next, the surface was oxidized (5.5 nm oxide) using a rapid thermal processing reactor chamber and circular geometry windows were opened in the oxide layer before metallization deposition; (2) the same as sequence (1) but with an additional in situ sputter etching step before metallization deposition; (3) cleaning in organic solvents followed by buffered HF dip. The I-V characteristics of Schottky diodes were analyzed to find a correlation between extracted parameters and surface treatment. The best results were obtained for the sequence (1) taking into account theoretical value of Schottky barrier height. The contacts showed excellent Schottky behavior with ideality factors below 1.08 and barrier heights of 1.46 eV and 1.64 eV for Ir and IrO₂, respectively. Very promising results were obtained for samples prepared using the sequence (2) taking into account the total static power losses because the modified surface preparation results in a decrease in the forward voltage drop and reverse leakage current simultaneously. The contacts with ideality factor below 1.09 and barrier height of 1.02 eV were fabricated for Ir/4H-SiC diodes in sequence (2).     

Temperature dependence of the current-voltage characteristics of the Al/Rhodamine-101/p-Si(1 0 0) contacts

The current-voltage (I-V) characteristics of Al/Rhodamine-101/p-Si/Al contacts have been measured at temperatures ranging from 280 to 400 K at 20 K intervals. A barrier height (BH) value of 0.817 eV for the Al/Rh101/p-Si/Al contact was obtained at the room temperature that is significantly larger than the value of 0.58 eV of the conventional Al/p-Si Schottky diode. While the barrier height Φ_b0 decreases the ideality factors (n) become larger with lowering temperature. The high values of n depending on the sample temperature may be ascribed to decrease of the exponentially increase rate in current due to space-charge injection into Rh101 thin film at higher voltage. Therefore, at all temperatures, it has been seen that the I-V characteristics show three different regions, the ohmic behavior at low voltages, and the space charge limited current with an exponential distribution of traps at high voltages.     

Investigation of electrical properties of organic 4-tricyanovinyl-N,N-diethylaniline thin film

Thin films of 4-tricyanovinyl-N,N-diethylaniline (TCVA) with different thickness were prepared using thermal evaporation technique. A relative permittivity, ?_r, of 3.04 was estimated from the dependence of capacitance on film thickness. The current density-voltage (J-V) characteristics of TCVA thin films have been investigated at different temperatures. At low-voltage region, the current conduction in the Au/TCVA/Au sandwich structures obeys Ohm's law. At the higher-voltage regions, the charge transport phenomenon appears to be space-charge-limited current (SCLC) dominated by an exponential distribution of traps with total trap concentration of 1.21 × 10²² m⁻³. In addition, various electrical parameters were determined.