Gadolinium oxide high-k gate dielectrics prepared by anodic oxidation

The growth and properties of gadolinium oxide (Gd₂O₃) films prepared by anodic oxidation were investigated. Uniform Gd₂O₃ thin film with good oxide quality was obtained. The X-ray diffraction (XRD) pattern of the Gd₂O₃ films showed that they had a poly-crystalline structure. The dielectric constants of Gd₂O₃ films oxidized at 30 and 60 V are 9.4 and 12.2, respectively. The equivalent oxide thickness (EOT) of the Gd₂O₃ stacked oxide is in the range of 5.8-9.4 nm. The MOS capacitor with Gd₂O₃ exhibits interesting electrical properties. Longer oxidation time reduced the leakage current density for 30 V anodic oxidation but increased the leakage current density for 60 V anodic oxidation. This work reveals that Gd₂O₃ could also be an alternative dielectric for Si substrate and therefore, might pave the way to fabricate CMOS devices in the future.     

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO₂/HfSiO/SiO₂ trilayer and HfTiSiO/SiO₂ bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO₂ underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO₂ capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10⁻² A/cm² for a TiO₂/HfSiO/SiO₂ trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.     

Electrical characteristics of polycrystalline Si layers embedded into high-k Al2O3 gate layers

The electrical characteristics of polycrystalline Si (poly Si) layers embedded into high-k Al₂O₃ (alumina) gate layers are investigated in this work. The capacitance versus voltage (C-V) curves obtained from the metal-alumina-polysilicon-alumina-silicon (MASAS) capacitors exhibit significant threshold voltage shifts, and the width of their hysteresis window is dependent on the range of the voltage sweep. The counterclockwise hysteresis observed in the C-V curves indicates that electrons originating from the p-type Si substrate in the inversion condition are trapped in the floating gate layer consisting of the poly Si layer present between the top and bottom Al₂O₃ layers in the MASAS capacitor. Also, current versus voltage (I-V) measurements are performed to examine the electrical characteristics of the fabricated capacitors. The I-V measurements reveal that our MASAS capacitors show a very low leakage current density, compared to the previously reported results.     

Characterization of gadolinium oxide film by pulse laser deposition

In this work, Gd-oxide dielectric films were deposited on Si by pulse laser deposition method (PLD), moreover, the micro-structures and electrical properties were reported. High-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD) indicated that Gd-oxide was polycrystalline Gd₂O₃ structure, and no Gd metal phase was detected. In addition, both interface at Si and Ni fully silicide (FUSI) gate were smooth without the formation of Si-oxide. X-ray photoelectron spectroscopy (XPS) confirmed the formation of Gd₂O₃ and gave an atom ratio of 1:1 for Gd:O, indicating O vacancies existed in Gd₂O₃ polycrystal matrix even at O₂ partial pressure of 20 mTorr. Electrical measurements indicated that the dielectric constant of Gd-oxide film was 6 and the leakage current was 0.1 A/cm² at gate bias of 1 V.     

Microstructure and dielectric properties of La2O3 doped amorphous SiO2 films as gate dielectric material

As a potential gate dielectric material, the La₂O₃ doped SiO₂ (LSO, the mole ratio is about 1:5) films were fabricated on n-Si (0 0 1) substrates by using pulsed laser deposition technique. By virtue of several measurements, the microstructure and electrical properties of the LSO films were characterized. The LSO films keep the amorphous state up to a high annealing temperature of 800 °C. From HRTEM and XPS results, these La atoms of the LSO films do not react with silicon substrate to form any La-compound at interfacial layer. However, these O atoms of the LSO films diffuse from the film toward the silicon substrate so as to form a SiO₂ interfacial layer. The thickness of SiO₂ layer is only about two atomic layers. A possible explanation for interfacial reaction has been proposed. The scanning electron microscope image shows the surface of the amorphous LSO film very flat. The LSO film shows a dielectric constant of 12.8 at 1 MHz. For the LSO film with thickness of 3 nm, a small equivalent oxide thickness of 1.2 nm is obtained. The leakage current density of the LSO film is 1.54 × 10⁻⁴ A/cm² at a gate bias voltage of 1 V.     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

Preparation of fluorocarbon thin film deposited by soft X-ray ablation and its electrical characteristics and thermal stability

Fluorocarbon films were deposited by soft X-ray ablation of polytetrafluoroethylene (PTFE) and characterized as low-dielectric-constant interlayer dielectrics. Very rapid deposition of such films at approximately 1500 nm/min could be achieved at room temperature. Fourier-transform infrared spectroscopy (FT-IR) measurement results suggest that the films deposited are primarily formed as one-dimensional chains of (-CF₂-)_n which are partially cross-linked. The cross-link density increases with increasing deposition temperature, which improves the thermal stability. However, the dielectric constant of the films increased abruptly above 300 °C. The dielectric constant and leakage current at 1.0 MV/cm of the film deposited at room temperature were approximately 2.1 and 2.0×10⁻⁹ A/cm², respectively.     

Chemical vapor deposition of ZrxTi1−xO2 and HfxTi1−xO2 thin films using the composite anhydrous nitrate precursors

Zr-Ti and Hf-Ti composite nitrates were successfully developed as single-source precursors for the chemical vapor deposition (CVD) of Zr_xTi_1−xO₂ and Hf_xTi_1−xO₂ thin films. The Zr-Ti nitrate can be assumed as a solid solution of the individual Zr and Ti nitrates, and the Zr/Ti molar ratio in the deposited Zr_xTi_1−xO₂ films is consistent with that in the precursor. The Hf-Ti nitrate appears to be a mixture of the Hf and Ti nitrates and the composition of the deposited Hf_xTi_1−xO₂ films depends remarkably on the heating time of precursor. Both Zr_xTi_1−xO₂ and Hf_xTi_1−xO₂ films exhibit trade-off properties between band gap and dielectric constant. The obtained results suggest that Zr_xTi_1−xO₂ and Hf_xTi_1−xO₂ films are promising candidates for gate dielectric application to improve the scalability and reduce the leakage current of the future complementary metal-oxide-semiconductor (CMOS) devices.     

HfO2/AlGaN/GaN structures with HfO2 deposited at ultra low pressure using an e‐beam

We show that HfO₂/AlGaN/GaN structures with HfO₂ layer deposited using an e‐beam in ultra high vacuum are suitable for field effect transistors. The dielectric constant of the HfO₂ was found ε_HfO > 23–24, which is close to the highest re‐ ported values for this material. The leakage current did not exceed 10^–4 A/cm² at the threshold voltage. The comparison of the losses in the samples with and without HfO₂ indicates low concentration of the interface traps. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Interface of anodic sulfide-oxide on n-type InSb

A novel anodic sulfidization process for forming native sulfide-oxide films on n-type InSb is described. The results of Auger electron spectroscopy analysis indicate that native sulfide-oxide films are formed from aqueous sulfide solutions. The measured capacitance-voltage characteristics of metal-insulator-semiconductor devices indicate that the films have a low fixed surface charge density of the order of 3×10¹⁰ cm^–2 and small hysteresis. The native sulfide-oxide films leave the surface of n-type InSb practically at flatband and in this respect are superior to the passivation layers of anodic oxide and direct plasma SiN _x . The interface between InSb and its native sulfide-oxide in combination with plasma CVD SiN _x has excellent electrical properties.     

Properties of high-k Ti1−xSixO2 gate dielectric layers prepared at room temperature

High-k Ti_1−xSi_xO₂ gate dielectric layers were prepared at room temperature by RF magnetron sputtering using SiO₂ and TiO₂ targets to investigate their applicability to transparent thin-film transistors as well as metal-oxide-semiconductor field-effect transistors. Based on XRD and XPS analyses, it was found that, regardless of the deposition time, the Ti_1−xSi_xO₂ gate dielectric layers had more stable Si-based phases with stronger Si-O bonds with increasing SiO₂ RF power. As SiO₂ RF power increased, the capacitance of the dielectric layers decreased due to the higher fraction of the Si-based phases, and the leakage current decreased, dominantly because of the decrease in oxygen vacancies due to the formation of stoichiometric SiO₂. The Ti_1−xSi_xO₂ gate dielectric layers exhibited high transparency above 80% and moderate bandgap of 4.1-4.2 eV, which can be applied to transparent thin-film transistors.     

Effect of Ti doping on Ta2O5 stacks with Ru and Al gates

The Ti-doped Ta₂O₅ thin films (<10 nm) obtained by rf sputtering are studied with respect to their composition, dielectric and electrical properties. The incorporation of Ti is performed by two methods - a surface doping, where a thin Ti layer is deposited on the top of Ta₂O₅ and a bulk doping where the Ti layer is sandwiched between two layers of Ta₂O₅. The effect of the process parameters (the method and level of doping) on the elemental distribution in-depth of the films is investigated by the time of flight secondary ion mass spectroscopy (ToF-SIMS). The Ti and Ta₂O₅ are intermixed throughout the whole thickness but the layers are very inhomogeneous. Two sub-layers exist in all the samples — a near interfacial region which is a mixture of Ta-, Ti-, Si-oxides as well as TaSiO, and an upper Ti-doped Ta₂O₅ sub-layer. For both methods of doping, Ti tends to pile-up at the Si interface. The electrical characterisation is performed on capacitors with Al- and Ru-gate electrodes. The two types of MIS structures exhibit distinctly different electrical behavior: the Ru gate provides higher dielectric permittivity while the stacks with Al electrode are better in terms of leakage currents. The specific metal-dielectric reactions and metal-induced electrically active defects for each metal electrode/high-k dielectric stack define its particular electrical behavior. It is demonstrated that the Ti doping of Ta₂O₅ is a way of remarkable improvement of leakage characteristics (the current reduction with more than four orders of magnitude as compared with undoped Ta₂O₅) of Ru-gated capacitors which originates from Ti induced suppression of the oxygen vacancy related defects.     

Effects of interface on the dielectric properties of Ba0.6Sr0.4TiO3 thin film capacitors

Ba_0.6Sr_0.4TiO₃ thin films were deposited on Pt/SiO₂/Si substrate by radio frequency magnetron sputtering. High-resolution transmission electron microscopy (HRTEM) observation shows that there is a transition layer at BST/Pt interface, and the layer is about 7-8 nm thickness. It is found that the transition layer was diminished to about 2-3 nm thickness by reducing the initial RF sputtering power. X-ray photoelectron spectroscopy (XPS) depth profiles show that high Ti atomic concentration results in a thick interfacial transition layer. Moreover, the symmetry ν of ?_r-V curve of BST thin film is enhanced from 52.37 to 95.98%. Meanwhile, the tunability, difference of negative and positive remanent polarization (P_r), and that of coercive field (E_C) are remarkably improved.     

PLD of X7R for thin film capacitors

Thin film capacitors with a thickness of 200 nm were prepared on SrTiO₃ (1 0 0), (1 1 0) and (1 1 1) single crystal substrates at a temperature of 973 K by pulsed laser deposition (PLD) using a KrF excimer laser in an O₂-O₃ atmosphere with a gas pressure of 1 Pa using an X7R sintered target. As a result, perovskite BaTiO₃ solid solution films were obtained. In the X7R thin films on (1 0 0) and (1 1 0) SrTiO₃, only diffraction peaks with strong intensities from BaTiO₃ (1 0 0) and (1 1 0), respectively, were observed. X7R films on SrTiO₃ (1 1 1) were grown epitaxially oriented to the crystal plane direction of the substrate by inserting an initial homoepitaxial SrTiO₃ layer with a thickness of 4 nm. The X7R/SrTiO₃ film capacitors yielded a large volumetric efficiency of 50 μF/mm³ and a temperature coefficient of capacitance (TCC) of −1.3% to 1.3% which satisfies the EIA standard specifications for X7R.     

Preparation of ZrO2 ultrathin films as gate dielectrics by limited reaction sputtering—On growth delay time at initial growth stage

ZrO₂ thin films were produced by limited reaction sputtering process varying the deposition parameters. An interesting growth phenomenon was observed in the initial growth stage of amorphous samples, appearing to suppress film growth for the first several minutes. The structures of such ultrathin ZrO₂ films were investigated by high-resolution Rutherford backscattering (HR-RBS) and X-ray photoelectron spectroscopy (XPS). The results suggest that the existence of interfacial suboxides due to the adsorption-induced surface reaction and diffusion-induced internal reaction, lead to the deteriorated interfacial performance. The mechanism and effects of the growth delay time on the interfacial characteristics are discussed in detail.     

Structural, dielectric and pyroelectric studies of Pb1−XCaXTiO3 thin films

Thin films of Pb_1−xCa_xTiO₃ [x=0.20, 0.24 and 0.28] have been prepared on ITO coated Corning glass substrates by sol gel technique. The perovskite phase of PCT films is formed at 650 °C with a polycrystalline tetragonal structure. The tetragonal factor (c/a) decreases with increasing Ca concentration. Dielectric, pyroelectric and ferroelectric studies have been carried out on these films. The effects of introduction of Ca ion in PbTiO₃ have also been discussed.     

Microstructural,dielectric and magnetic behavior of spin-deposited nanocrystalline nickel–zinc ferrite thin films for microwave applications

Nanocrystalline nickel ferrite and zinc doped nickel ferrite thin films with general composition Ni_1−xZn_xFe₂O₄; x=0.0, 0.2 and 0.5 were fabricated by the spin-deposition technique. Citrate precursor method was adopted to prepare coating solution used for film deposition. This method resulted in single phase, transparent, homogeneous and crack-free nanocrystalline ferrite thin films at annealing temperature as low as 400 °C. The substrates used for film deposition were ITO-coated 7059 glass, fused quartz and Si (1 0 0). The thickness of films was found to be in the range ∼1000–5500 Å. The surface microstructure and morphology investigated by atomic force microscopy (AFM) confirmed the grain size of nickel–zinc ferrite films to be in nanometer range indicating nanocrystalline nature of the films. Dielectric properties such as the real (∈′) and imaginary parts (∈″) of complex permittivity were measured in the X-band microwave frequency region (8–12 GHz) by employing extended cavity perturbation technique. The M–H hysteresis measurements on the films annealed at 650 °C revealed narrow hysteresis curves with H_c and M_s varying for different compositions.     

Band bending measurement of HfO2/SiO2/Si capacitor with ultra-thin La2O3 insertion by XPS

The flat band voltage shifts of HfO₂/SiO₂/nSi capacitors with ultra-thin La₂O₃ insertion at HfO₂/SiO₂ interface have been confirmed using hard X-ray photoelectron spectroscopy (HX-PES). By increasing the amount of La₂O₃ insertion, the binding energy of Si 1s core spectra increases, which means that the surface potential of Si substrate also increases. A voltage drop difference of HfO₂ and La₂O₃ at SiO₂ interface can be estimated to be 0.40 V.     

Advance in next Century nanoCMOSFET research

It is well known that Taiwan's IC industry is in the very leading front of the world, and production of 65 nm devices was launched in 2006. Within a few years, the need of high-k dielectrics and metal gates is eminent and truly indispensable. Professor H.L. Hwang (the author) organized 12 professors and 50 graduate students of National Tsing Hua University and Chiao Tung University, and executed this particular project, which is sponsored by the Ministry of Economic Affairs of Republic of China, and is aimed at treating efficiently this problem and transferred the critical technologies to industry in a time frame of 3 years.     

Trap-controlled behavior in ultrathin Lu2O3 high-k gate dielectrics

Amorphous Lu₂O₃ high-k gate dielectrics were grown directly on n-type (100) Si substrates by the pulsed laser deposition (PLD) technique. High-resolution transmission electron microscope (HRTEM) observation illustrated that the Lu₂O₃ film has amorphous structure and the interface with Si substrate is free from amorphous SiO₂. An equivalent oxide thickness (EOT) of 1.1 nm with a leakage current density of 2.6×10⁻⁵ A/cm² at 1 V accumulation bias was obtained for 4.5 nm thick Lu₂O₃ thin film deposited at room temperature followed by post-deposition anneal (PDA) at 600 °C in oxygen ambient. The effects of PDA process and light illumination were studied by capacitance-voltage (C-V) and current density-voltage (J-V) measurements. It was proposed that the net fixed charge density and leakage current density could be altered significantly depending on the post-annealing conditions and the capability of traps to trap and release charges.