Secure Classical Bit Commitment Using Fixed Capacity Communication Channels

If mutually mistrustful parties A and B control two or more appropriately located sites, special relativity can be used to guarantee that a pair of messages exchanged by A and B are independent. In earlier work we used this fact to define a relativistic bit commitment protocol, RBC1, in which security is maintained by exchanging a sequence of messages whose transmission rate increases exponentially in time. We define here a new relativistic protocol, RBC2, which requires only a constant transmission rate and could be practically implemented. We prove that RBC2 allows a bit commitment to be indefinitely maintained with unconditional security against all classical attacks. We examine its security against quantum attacks, and show that it is immune from the class of attacks shown by Mayers and Lo-Chau to render non-relativistic quantum bit commitment protocols insecure.     

Testing second-order delta-sigma modulators using pseudo-random patterns

Single-bit second-order delta-sigma modulators are commonly used in high-resolution analog-to-digital converters (ADCs). This type of modulator requires high-resolution test stimulus, which is difficult to generate. This paper proposes a novel and robust technique to determine the performance of the modulator by characterizing its key parameters using a pseudo-random pattern sequence. This technique is suitable for BIST application since a pseudo-random sequence can be generated on-chip using LFSR. Numerical simulation results show that this technique is capable of identifying parameters that affect the performance of a second-order delta-sigma modulator ADC.     

Bit commitment using pseudorandomness

We show how a pseudorandom generator can provide a bit-commitment protocol. We also analyze the number of bits communicated when parties commit to many bits simultaneously, and show that the assumption of the existence of pseudorandom generators suffices to assure amortized O(1) bits of communication per bit commitment.Part of this work was done while the author was at the University of California at Berkeley. This research was supported by NSF Grant CCR 88-13632.     

产生2k元伪随机序列的准混沌Mealy型有限状态机方法

该文利用m状态序列稳定的长周期，以及混沌序列流的高线性复杂度，研究了一种将m状态序列作为准混沌Mealy型有限状态机输入的2k元伪随机序列产生方法，分析了系统的周期待性，进行了序列流随机性的测试，介绍了系统作为跳频码发生器在FPGA的仿真和综合结果．     

An efficient bit commitment scheme based on factoring assumption

Recently, many bit commitment schemes have been presented. This paper presents a new practical bit commitment scheme based on Schnorr's one-time knowledge proof scheme, where the use of cut-and-choose method and many random exam candidates in the protocols are replaced by a single challenge number. Therefore the proposed bit commitment scheme is more efficient and practical than the previous schemes. In addition, the security of the proposed scheme under factoring assumption is proved, thus the cryptographic basis of the proposed scheme is clarified.     

A ring oscillator based frequency synthesizer without using frequency divider

A novel indirect frequency synthesizer (FS) circuit comprising a multiplexer (MUX) controlled ring oscillator (RO) and a Hogge phase detector has been proposed. The circuit will synthesize signals having better spectral purity and will consume less power compared to conventional indirect FS circuits. The MUX controlled RO will provide higher flexibility in frequency control and the voltage controlled oscillator (VCO) sensitivity can be varied easily to keep loop gain fixed for different values of synthesized signal frequencies. Hardware experimental results have been given to establish theoretical anticipations.     

基于椭圆曲线的三方比特承诺

比特承诺是安全多方计算中最重要的基础协议之一,对构建更复杂的多方协议起着重要作用。该文提出了三方比特承诺模型,在该模型中,由两个证明者共同向一个验证者作出承诺。给出了基于椭圆曲线的三方比特承诺方案,经证明,尽管该方案完全基于经典计算环境,但是并不需要对协议参与方的计算能力作任何限制性假设,具有无条件安全性且对信道窃听免疫。该方案同时可以推广到比特串承诺协议。     

A fast lock frequency synthesizer using an improved adaptive frequency calibration

An improved adaptive frequency calibration (AFC) has been employed to implement a fast lock phase-locked loop based frequency synthesizer in a 0.18 μm CMOS process. The AFC can work in two modes: the frequency calibration mode and the store/load mode. In the frequency calibration mode, a novel frequency-detector is used to reduce the frequency calibration time to 16 μs typically. In the store/load mode, the AFC makes the voltage-controlled oscillator (VCO) return to the calibrated frequency in about 1 μs by loading the calibration result stored after the frequency calibration. The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is -82 dBc/Hz. The lock time is about 20 μs in frequency calibration mode and about 5 μs in store/load mode. The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.     

一种用于MB-OFDM 超宽带的低杂散快速跳频的频率综合器

本文设计了一种应用于超宽带第一频率组的频率综合器。该频率综合器采用锁相环和单边带混频器,将4224MHz分别与±264MHz和+792MHz混频来产生第一频率组的三个中心频率。并且设计了一个新颖的多模式正交单边带混频器,它集合了选频与混频的功能,将线性度提高并且降低了功耗。芯片通过Jazz 0.18-μm RF CMOS工艺流片,测试结果显示其输出频谱干净,参考时钟杂散只有-69dBc,最大的杂散是LO泄漏为-32dBc。它的相位噪声为-110dBc/Hz@1MHz,并且积分相位噪声只有1.86°。当频率发生跳变时,跳频时间约为1.8ns。整个芯片工作在1.8V电源电压,消耗30mA电流。     

A low-spurious fast-hopping MB-OFDM UWB synthesizer

A frequency synthesizer for the ultra-wide band(UWB)group # 1 is proposed.The synthesizer uses a phase locked loop(PLL)and single-sideband(SSB)mixers to generate the three center frequencies of the first band group by mixing 4224 MHz with ±264 MHz and 792 MHz,respectively.A novel multi-QSSB mixer is designed to combine the function of frequency selection and frequency conversion for low power and high linearity.The synthesizer is fabricated in Jazz 0.18-μm RF CMOS technology.The measured reference spur is as low as-69 dBc and the maximum spur is the LO leakage of-32 dBc.A low phase noise of-110 dBc/Hz @ 1 MHz offset and an integrated phase noise of 1.86°are achieved.The hopping time between different bands is less than 1.8 ns.The synthesizer consumes 30 mA from a1.8 V supply.     

具有改进型自适应频率校准的快速锁定频率综合器

本文介绍了一种具有改进型自适应频率教准（AFC）模块的快速锁定锁相环型频率综合器,该综合器使用0.18ucm CMOS工艺实现。AFC的工作模式有两种：频率校准模式和存储/加载模式。频率校准模式使用了一种新型的鉴频器可以把频率校准时间缩短到16uS。在存储/加载模式下,通过保存频率校准后的结果并且在需要时加载,AFC可在1uS内使压控振荡器（VCO）的频率恢复为校准过的频率点。测试结果显示,VCO的谐振范围为620~920MHz;在环路带宽为10kHz时,锁相环带内噪声为-82dBc/Hz;频率校准模式下的锁定时间为20uS而存储/加载模式下为5uS;在1.8V供电下,锁定后频率综合器的工作电流为12mA。     

一种先进的N分数锁相环频率合成器

分析了N分数PLL频率合成器，并把 Σ-Δ调制技术应用于频率合成器中，解决了频率分辨率和鉴相器工作频率之间的矛盾，同时大大提高了噪声性能。     

频率源设计中参考信号多路功分处理技术

复杂频率源系统,其参考信号需要进行多路功分处理,该处理会对参考信号的相位噪声产生影响。文章针对参考信号功分放大带来的相位噪声恶化现象,给予了详细的理论分析,并结合实例,给出适合工程需要的解决方法,工程实践中验证了该方法的有效性。     

射频锁相频率合成器的设计与仿真

频率合成器可以提供大量精确、稳定的频率作为无线通信设备的本振信号。简要介绍了锁相环频率合成器的基本原理,并利用整数N锁相芯片ADF4112设计了一个宽波段的频率合成器。讨论了其中主要元器件的选择和环路滤波器的设计,利用先进设计系统(Advanced Design System,ADS)仿真软件对设计方案进行频域和瞬态响应仿真,并使用其中的优化工具对各个参数进行优化。仿真与优化结果验证了频率合成器的可行性,同时可以得到优化后环路滤波器的参数。     

基于∑-△调制小数分频技术的频率合成器MAX2150及其应用

介绍了基于∑-△调制器的小数分频(F-N)频率合成技术的基本原理及采用此技术的频率合成器MAX2150,给出了MAX2150在某微波测试仪表中的应用电路和注意事项.     

A low power fast-settling frequency-presetting PLL frequency synthesizer

This work presents the design and implementation of a 2.4 GHz low power fast-settling frequency-presetting PLL frequency synthesizer in the 0.18μm CMOS process.A low power mixed-signal LC VCO,a low power dual mode prescaler and a digital processor with non-volatile memory are developed to greatly reduce the power consumption and the setting time.The digital processor can automatically calibrate the presetting frequency and accurately preset the frequency of the VCO under process variations.The experiment...     

基于MATLAB的锁相环频率合成器教学实践

通信系统性能好坏很大程度上取决于有没有一个良好的同步系统。在“通信原理”课程中提到了基于锁相环的同步系统,但是对这部分内容介绍简单,没有系统的推导以及结论。基于Matlab的锁相环系统,能够得到不同参数下的锁相环的环路滤波器幅频响应和闭环响应,在Simulink工具箱中,设计一个基于锁相环的频率合成器,让学生掌握锁相环相位锁定的原理以及同步系统,为通信原理课程学习提供了支持。     

MC145163P型锁相频率合成器的原理与应用

Motolora公司的MC145163P是CMOS大规模集成锁相频率合成器,内部含有参考分频器、两个相位比较器和4位BCD/N分频器,配合环路滤波和压控振荡器就可以得到一个完整、实用的锁相频率合成器.文中介绍了MC145163P的基本性能,并结合实际应用详细介绍了由MC145163P和TTL压控振荡器74LS628组成的锁相频率合成电路,给出实际测量数据.     

一种低功耗频率预置快速锁定的锁相环频率综合器

本文提出了一种2.4GHz低功耗频率预置快速锁定的锁相环频率综合器,该频率综合器使用0.18um 的CMOS 工艺制作。设计了低功耗的混合信号压控振荡器,双模预置分频器,数字处理器和非易失性存储器来降低整体系统的功耗和减小锁定时间。数字处理器可以在工艺偏差的情况下自动的校正压控振荡器的预置频率,使得对振荡器频率的预置可以达到很高的精度。测试结果表明,在1.8V 的电源电压下,频率综合器的电流消耗为4mA,它的典型的锁定时间小于3us。