超深亚微米PMOS器件的NBTI退化机理

对超深亚微米PMOS器件的负栅压温度不稳定性(NBTI)退化机理进行了研究.主要集中在对器件施加NBT和随后的PBT应力后器件阈值电压的漂移上.实验证明反型沟道中空穴在栅氧中的俘获以及氢分子在栅氧中的扩散是引起NBTI退化的主要原因.当应力条件变为PBT时，陷落的空穴可以快速退陷，但只有部分氢分子可以扩散回栅氧与衬底界面钝化硅悬挂键，这就导致了PBT条件下阈值电压只能部分恢复. 关键词： 超深亚微米PMOS器件 负偏压温度不稳定性 界面陷阱 氢气     

0.25-μm PMOSFETs中热载流子的退化特性和解释

本文研究了深亚微米PMOSFETs的热载流子效应。研究发现热载流子效应包括界面态的产生和氧化层中固定正电荷的形成。通过实验证明了深亚微米PMOSFETs中这两种机制的重要性。首先，氧化层固定正电荷的产生在深亚微米PMOSFETs中起作用，使得器件的阈值电压退化，最终限制了表面沟道晶体管的使用寿命。对于先进的模拟和混合信号的应用，工艺和器件的可靠性必须按照阈值电压的漂移重新定义，而不仅仅依照跨导的退化或者栅氧化层的寿命来定义。其次，空穴注入产生的界面态也影响器件的特性。推断了热载流子效应的形成过程。     

新型槽栅PMOSFET热载流子退化机理与抗热载流子效应研究

分析了槽栅器件中的热载流子形成机理,发现在三个应力区中,中栅压附近热载流子产生概率达到最大.利用先进的半导体器件二维器件仿真器研究了槽栅和平面PMOSFET的热载流子特 性,结果表明槽栅器件中热载流子的产生远少于平面器件,且对于栅长在深亚微米和超深亚 微米情况下尤为突出.为进一步探讨热载流子加固后对器件特性的其他影响,分别对不同种 类和浓度的界面态引起的器件栅极和漏极特性的漂移进行了研究,结果表明同样种类和密度 的界面态在槽栅器件中引起的器件特性的漂移远大于平面器件.为开展深亚微米和亚0.1微米 新型槽栅 关键词： 槽栅PMOSFET 热载流子退化机理 热载流子效应     

pMOS器件直流应力负偏置温度不稳定性效应随器件基本参数变化的分析

应用负偏置温度不稳定性(negative bias temperature instability,NBTI),退化氢分子的漂移扩散模型,与器件二维数值模拟软件结合在一起进行计算,并利用已有的实验数据和基本器件物理和规律,分析直流应力NBTI效应随器件沟道长度、栅氧层厚度和掺杂浓度等基本参数的变化规律,是研究NBTI可靠性问题发生和发展机理变化的一种有效方法.分析结果显示,NBTI效应不受器件沟道长度变化的影响,而主要受到栅氧化层厚度变化的影响;栅氧化层厚度的减薄和栅氧化层电场增强的影响是一致的,决定了器件退化按指数规律变化;当沟道掺杂浓度提高,NBTI效应将减弱,这是因为器件沟道表面空穴浓度降低引起的;然而当掺杂浓度提高到器件的源漏泄漏电流很小时(小泄露电流器件),NBTI效应有明显的增强.这些结论对认识NBTI效应的发展规律以及对高性能器件的设计具有重要的指导意义.     

超薄栅下LDD nMOSFET器件GIDL应力下退化特性

对1.4nm超薄栅LDD nMOSFET器件栅致漏极泄漏GIDL(gate-induced drain leakage)应力下的阈值电压退化进行了研究.GIDL应力中热空穴注进LDD区界面处并产生界面态，这导致器件的阈值电压变大.相同栅漏电压V_DG下的不同GIDL应力后阈值电压退化量的对数与应力V_D/V_DG的比值成正比.漏偏压V_D不变的不同GIDL应力后阈值电压退化随着应力中栅电压的增大而增大，相同栅偏压V_G下的不同GIDL应力后阈值电压退化也随着应力中漏电压的增大而增大，这两种应力情形下退化量在半对数坐标下与应力中变化的电压的倒数成线性关系，它们退化斜率的绝对值分别为0.76和13.5.实验发现器件退化随着应力过程中的漏电压变化远大于随着应力过程中栅电压的变化. 关键词： 栅致漏极泄漏 CMOS 阈值电压 栅漏电压     

工艺偏差下PMOS器件的负偏置温度不稳定效应分布特性

当器件特征尺寸进入纳米级,负偏置温度不稳定性(NBTI)效应和工艺偏差都会导致p型金属氧化层半导体(PMOS)器件性能和可靠性的下降.基于反应-扩散(R-D)模型,本文分析了工艺偏差对NBTI效应的影响;在此基础上将氧化层厚度误差和初始阈值电压误差引入到R-D模型中,提出了在工艺偏差下PMOS器件的NBTI效应统计模型.基于65 nm工艺,首先蒙特卡罗仿真表明在工艺偏差和NBTI效应共同作用下,PMOS器件阈值电压虽然会随着应力时间增大而沿着负方向增加,但是阈值电压的匹配性却随着时间推移而变好;其次验证本文提出的统计模型准确性,以R-D模型为参考,在10~4s应力时间内,PMOS器件阈值电压退化量平均值和均方差的最大相对误差分别为0.058%和0.91%;最后将此模型应用到电流舵型数模转换器中,仿真结果显示在工艺偏差和NBTI效应共同作用下,数模转换器的增益误差会随着应力时间的推移而增大,而线性误差会逐渐减小.     

具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO₂高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中，负 偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO₂高K栅结构的等效 氧化层厚度(EOT)为1.3nm，内含原生缺陷密度较低.研究表明，由于所制备的HfN/HfO₂ 高K栅结构具有低的原生缺陷密度，因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征，而非工艺缺陷引起的；进一步研究表明，该HfN/HfO₂高K栅结构中观察到的NBTI与传统的SiO₂基栅介质p-MOSFET器件中观察 到的NBTI具有类似的特征，可以被所谓的反应-扩散(R-D)模型表征： HfN/HfO₂ 栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理，即在负 偏置和温度应力作用下，从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的 发生，并由此产生了Si^＋陷阱在Si衬底界面的积累和H原子在介质层内部的扩散 ，这种Si^＋陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生. 关键词： 高K栅介质 负偏置-温度不稳定性(NBTI) 反应-扩散(R-D)模型     

Snapback应力引起的90 nm NMOSFET's栅氧化层损伤研究

实验结果发现突发击穿(snapback)，偏置下雪崩热空穴注入NMOSFET栅氧化层，产生界面态，同时空穴会陷落在氧化层中.由于栅氧化层很薄，陷落的空穴会与隧穿入氧化层中的电子复合形成大量中性电子陷阱，使得栅隧穿电流不断增大.这些氧化层电子陷阱俘获电子后带负电，引起阈值电压增大、亚阈值电流减小.关态漏泄漏电流的退化分两个阶段：第一阶段亚阈值电流是主要成分，第二阶段栅电流是主要成分.在预加热电子(HE)应力后，HE产生的界面陷阱在snapback应力期间可以屏蔽雪崩热空穴注入栅氧化层，使器件snapback开态和关态特性退化变小. 关键词： 突发击穿 软击穿 应力引起的泄漏电流 热电子应力     

超深亚微米PMOSFET的自愈合效应

主要研究负栅压偏置不稳定性(negative bias temperature instability，NBTI)效应中的自愈合效应，研究了器件阈值电压随着恢复时间和应力时间的恢复规律.研究表明器件的退化可以恢复是由于NBTI应力后界面态被氢钝化. 关键词： 负偏置温度不稳定性效应 自愈合效应 应力时间 PMOSFET     

具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO2高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中,负偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO2高K栅结构的等效氧化层厚度(EOT)为1.3nm,内含原生缺陷密度较低.研究表明,由于所制备的HfN/HfO2高K栅结构具有低的原生缺陷密度,因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征,而非工艺缺陷引起的;进一步研究表明,该HfN/HfO2高K栅结构中观察到的NBTI与传统的SiO2基栅介质p-MOSFET器件中观察到的NBTI具有类似的特征,可以被所谓的反应-扩散(R-D)模型表征: HfN/HfO2栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理,即在负偏置和温度应力作用下,从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的发生,并由此产生了Si+陷阱在Si衬底界面的积累和H原子在介质层内部的扩散,这种Si+陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生.     

The role of hydrogen in negative bias temperature instability of pMOSFET

The NBTI degradation phenomenon and the role of hydrogen during NBT stress are presented in this paper. It is found that PBT stress can recover a fraction of V_th shift induced by NBTI. However, this recovery is unstable. The original degradation reappears soon after reapplication of the NBT stress condition. Hydrogen-related species play a key role during a device's NBT degradation. Experimental results show that the diffusion species are neutral, they repassivate Si dangling bond which is independent of the gate voltage polarity. In addition to the diffusion towards gate oxide, hydrogen diffusion to Si-substrate must be taken into account for it also has important influence on device degradation during NBT stress.     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

Reduction of charge trapping in HfO2 film on a Ge substrate by trimethylaluminum pretreatment

Trimethylaluminum pretreatment prior to HfO₂ deposition is introduced for native oxide reduction. It is identified that the trimethylaluminum pretreatment could effectively reduce native oxide, which is transformed to an aluminum oxide interfacial layer. Formation of the thin aluminum oxide layer suppresses Ge diffusion into HfO₂, reducing hysteresis in the ca‐ pacitance–voltage curve. Moreover, the device reliability of the trimethylaluminum pretreated sample is improved in a constant current stress test. This work indicates that trimethylaluminum pretreatment is an effective in‐situ method for the gate dielectric stack formation to reduce charge trapping in the HfO₂ film on a Ge substrate. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

On the influence of interfaces and localised stress fields on irradiation-induced point-defect distributions in silicon

High-flux 1-MeV electron irradiation in a high voltage transmission electron microscope is used to study the influence of interfaces and localised stress fields on {113}-defect generation in silicon. A semi-quantitative model is presented to explain the observations, suggesting that the silicon oxide/silicon interface is a stronger sink for self-interstitials than for vacancies. It is shown that the position and the height of the maximum of the {113}-defect density strongly depends on the strength of the interface as a vacancy sink and that compressive straining of the silicon substrate slows down the diffusion of vacancies towards the interface.     

Impact of STI indium implantation on reliability of gate oxide

The impacts of shallow trench isolation(STI)indium implantation on gate oxide and device characteristics are studied in this work.The stress modulation effect is confirmed in this research work.An enhanced gate oxide oxidation rate is observed due to the enhanced tensile stress,and the thickness gap is around 5%.Wafers with and without STI indium implantation are manufactured using the 150-nm silicon on insulator(SOI)process.The ramped voltage stress and time to breakdown capability of the gate oxide are researched.No early failure is observed for both wafers the first time the voltage is ramped up.However,a time dependent dielectric breakdown(TDDB)test shows more obvious evidence that the gate oxide quality is weakened by the STI indium implantation.Meanwhile,the device characteristics are compared,and the difference between two devices is consistent with the equivalent oxide thickness(EOT)gap.     

纳米颗粒的表面效应和电极颗粒间挤压作用对锂离子电池电压迟滞的影响

硅作为锂离子电池电极材料之一,其应力效应尤为突出,进而将影响电池性能.本文建立了电化学反应-扩散-应力全耦合模型,并研究了恒压充放电条件下扩散诱导应力、表面效应和颗粒间挤压作用对电压迟滞的影响.结果发现,应力及其导致的电压迟滞程度与颗粒尺寸相关.在大颗粒(颗粒半径r 100 nm)中,扩散诱导应力是导致电势迟滞效应的主要因素,这将导致电池能量耗散.对于纳米级小颗粒(r 100 nm)而言,表面效应占据主导,表面效应虽然能缓解电压迟滞,同时却会使驱动电化学反应部分的过电势回线下移,造成锂化容量衰减.本文综合考虑了扩散诱导应力和表面效应,得出:半径为10 nm的颗粒将会使电极具备较好的综合性能.此外,对于硅电极而言,颗粒间挤压作用会使应力回线向压应力状态演化,进而导致锂化容量的衰减.计算结果表明,在电极设计中,对孔隙率设定下限值有助于提升电极性能.