仪器漏电引起的CMOS电路闩锁

以某整机在调试过程中发生的一只CMOS驱动门电路的闰锁失效为例，具体分析了测试仪器感应漏电引起CMOS电路闩锁的现象、机理和原因，具有一定的典型性。     

基于漏电流补偿技术的超低漏电模拟开关

为满足各种现代设备控制系统的超高精度信号采集需求,基于新型PN结漏电补偿技术设计了一种超低漏电模拟开关电路。该电路在传统CMOS模拟开关的基础上创新性地引入了新型全温区PN漏电采样和补偿电路,对CMOS模拟开关输入、输出漏电流进行全温区漏电补偿,大幅降低了输入、输出端口漏电流,实现亚纳安级端口漏电流。基于40 V高压CMOS工艺进行电路设计和仿真验证,实测结果显示,在-55～125℃,输入、输出端口漏电流不大于0.75 nA,温漂约为6 pA/℃。     

静态随机存取存储器漏电流功耗降低技术

分析了静态随机存取存储器 (SRAM) 的漏电流,总结了目前业界所用的各种降低漏电流的技术,包括衬底偏压、源极偏压、双电源电压、字线电压反偏和位线电压浮动结构.它们都是通过改变SRAM各个端点的电压来实现的,在降低漏电流的同时,对SRAM器件性能也有一定的影响.基于UMC 55 nm CMOS工艺,对几种方案进行了仿真,并在理论分析的基础上,指出未来发展的趋势.     

纳米CMOS电路逻辑等效变换

针对纳米CMOS电路连通域结构约束,该文提出了基于逻辑复制方法的电路等效变换技术以降低电路映射复杂性。首先通过对电路中所有的门扇出值进行排序来选定基准高扇出值;然后对于高扇出门单元通过二次方程式计算变换前后复杂度,对复杂度降低的高扇出门单元执行逻辑复制并进行扇出分割。与传统插入反相器方法网表转换法比较,结果表明使用该文提出的方法电路不仅更快速地被映射到纳米混合电路单元上,而且具有更好的时延特性。     

CMOS电路的最大动态功耗计算和测试生成＊

本文首先提出,CMOS电路的最大动态功耗计算,可以通过计算在特定输入序列作用下电路中的不变门数的最小值来实现。本文提出的极性推导、赋值法可以快速求解不变门数的最小值,并生成相应的输入序列。该算法与电路的输入变量数无关。     

超深亚微米CMOS工艺参数波动的测量电路

分析了超深亚微米工艺参数波动对电路的影响;采用"放大"的思路设计了简单的用于测量超深亚微米工艺门延迟、动态功耗、静态功耗及其波动的电路,并提出了一种用于测量门延迟波动特性曲线的新型电路,该电路采用较短的反相器链可以得到超深亚微米工艺下门延迟波动特性曲线.电路在90nm CMOS工艺下进行了流片制作,得到了90nm CMOS工艺下的单位门延迟波动特性曲线.测得延迟的波动范围为78.6%,动态功耗的波动范围为94.0%,漏电流功耗的波动范围为19.5倍,其中以漏电流功耗的波动性最为严重.     

超深亚微米CMOS工艺参数波动的测量电路

分析了超深亚微米工艺参数波动对电路的影响;采用"放大"的思路设计了简单的用于测量超深亚微米工艺门延迟、动态功耗、静态功耗及其波动的电路,并提出了一种用于测量门延迟波动特性曲线的新型电路,该电路采用较短的反相器链可以得到超深亚微米工艺下门延迟波动特性曲线.电路在90nm CMOS工艺下进行了流片制作,得到了90nm CMOS工艺下的单位门延迟波动特性曲线.测得延迟的波动范围为78.6%,动态功耗的波动范围为94.0%,漏电流功耗的波动范围为19.5倍,其中以漏电流功耗的波动性最为严重.     

CMOS电路的低功耗设计技术

ＣＭＯＳ集成电路随着规模和速度的迅速提高以及在便携式电子产品中的广泛应用，电路功耗已成人们关注的关键问题。本文重点叙述了降低ＣＭＯＳ电路功耗的主要途径和低功耗设计技巧。     

Power dissipation sources and possible control techniques in ultra deep submicron CMOS technologies

As technology scales down into the ultra deep-submicron (UDSM) region, the static power dissipations grow exponentially and become an increasingly dominant component of the total power dissipation in CMOS circuits. With increase in gate leakage current resulting from thinner gate oxides in UDSM and the problems associated with short channel effects, leakage power dissipation is becoming a huge factor challenging a continuous success of CMOS technology in the semiconductor industry. With strict limitations of maximum allowable power (the power being limited more by system level cooling and test constraints than packaging) of 2.8 W (in 2005) to 3 W (in 2020) for battery (low cost/handheld) operated devices as projected by the International Technology Roadmap for Semiconductors (ITRS) 2005, innovations in leakage control and management are urgently needed. This paper presents an overview of the sources of the power dissipation mechanisms in the UDSM technologies, and the device and circuit techniques to control them.     

Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits

介绍一种简单而有效的提高集成电路稳定性的电路补偿方法.当电路制造过程中的工艺参数、工作电压或工作温度发生变化时,根据仿真结果,该方法可以使MOS晶体管跨导的标准差比未经补偿的电路降低41.4%.这种电路可以用于CMOS LC振荡器中.     

用于降低CMOS集成电路中晶体管跨导标准差的偏置电流补偿电路

介绍一种简单而有效的提高集成电路稳定性的电路补偿方法.当电路制造过程中的工艺参数、工作电压或工作温度发生变化时,根据仿真结果,该方法可以使MOS晶体管跨导的标准差比未经补偿的电路降低41.4%.这种电路可以用于CMOS LC振荡器中.     

SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS

Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-V_th) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-V_th devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-V_th devices are desired in the read port for implementing higher performance. However, excessively raised V_th in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65 nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.     

CMOS时序逻辑电路功耗估计的一种新方法

MOS时序逻辑电路由于存在时序反馈环，使功耗分析变得相当复杂。文章提出了一种采用电路化简加速功耗估计的方法。对ISCAS’89和ISCAS’93基本测试电路的实验结果表明，此方法具有较好的计算精度和较短的计算时间。     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.     

毫米波CMOS集成电路的现状与趋势

随着深亚微米和纳米CMOS工艺的成熟,设计和实现低成本的毫米波CMOS集成电路已成为可能.简述了毫米波CMOS技术的发展现状,介绍了毫米波CMOS集成电路的关键技术,即晶体管建模和传输线建模,并给出了毫米波CMOS电路的最新进展和发展趋势.     

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

纳米集成电路静态功耗机理及低功耗设计技术

对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述．以期为相关研究：设计人员提供有益参考。