并行多处理机系统中的光纤互连网络的设计与实现

在并行多处理机系统中应用光纤互连网络完成处理单元之间的数据交换,可以极大地提高系统中数据通信的速率、带宽、抗干扰性和准确可靠性.本文详细阐述了并行多处理机系统的体系结构、实现方法、性能分析和实验结果.     

GF11

GF11 is a parallel processor currently under construction at the IBM Yorktown Research Center. The machine incorporates 576 floating-point boards. Each board has space for 2 × 10⁶ bytes of memory and is capable of 2 × 10⁷ floating point operations per second, given the total machine a peak of 1.15 × 10⁹ bytes of memory and 1.15× 10¹⁰ floating point operations per second. The floating-point processors are interconnected by a dynamically reconfigurable switching network. At each machine cycle any of 1024 preselected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chormodynamics.     

Reconfigurable architectures for parallel execution of image processing tasks

Reconfigurable computers are becoming third, after general purpose processors and digital signal processors, programmable computing systems. In the present paper, a new definition of parallelism adequate for fine-grain parallel systems is introduced. Computing power requirements for high definition, real-time vision system are discussed. A survey of reconfigurable solutions for image processing and the latest research work carried on at the AGH Laboratory of Biocybernetics are presented.     

Reconfigurable all-optical logic gate using four-wave mixing (FWM) in HNLF for NRZ-PolSK signal

We demonstrate a reconfigurable all-optical logic gate for NRZ-PolSK signal based on FWM in a highly nonlinear fiber at 10 Gb/s. Half subtracter, XOR, AB?, āB or XNOR, AND, and NOR logic gates can be implemented simultaneously. The input power for the HNLF is optimized to be as low as about 15.2 dBm and the high Q factors above 8 dB for eye diagrams are achieved. Experimental results show Q factors of AB?, āB, AND, and NOR were higher than those of XOR, and XNOR. Error-free operation is achieved experimentally for 10 Gb/s 2⁷-1 pseudorandom bit sequence (PRBS) data. Power penalties for the logic gate are less than 3 dB. Simulation analysis about the wavelength characteristic for all logic gates is given and it predicts that the reconfigurable logic gate can realize error-free operation when the wavelength separation is less than 5 nm.     

Twin-Ring Optical WDM-MAN Enabling Triple-Hierarchical Reconfigurations and Quadruple-Shared Protections

An optical wavelength division multiplexing metro access network is proposed in this paper. With the design of flexible distribution node (FDN), three kinds of reconfigurable networks can be flexibly built to achieve intra- and inter-optical network unit (ONU)-direct communications. With the adoption of multiple tangent twin-ring topologies, four-level shared protections covering both feeder and distribution fibers are also supported. Moreover, the network can be smoothly expanded by adding express ONUs connected to FDNs. Thus, the network can not only achieve capacity increasing but also support full-duplex reconfigurable communication. A reconfigurable transmission algorithm is also set to avoid wavelengths conflict.     

Critical phenomena in discrete-time interconnection networks

We present theoretical and numerical results for the performance of a multiprocessor network modeled as a ring and as a toroidal square lattice of nodes with local processors that generate messages for output ports/buffers. The output buffers are assumed to have infinite capacity, and the service time is deterministic. Two models are considered. One assumes that every processor generates messages with rate λ per time slot and per output port/buffer. The other model considers that the generation rate of a node depends on the intensity of the flow of arriving messages. Explicit expressions for the distribution of queue lengths, the average number of messages in the buffers, the average latency, and the critical network load depending on the distance between the source and the destination are obtained. Simulation results show excellent agreement with theoretical predictions based on the assumption of independent queues.     

A fast mesh deformation method using explicit interpolation

A novel mesh deformation algorithm for unstructured polyhedral meshes is developed utilizing a tree-code optimization of a simple direct interpolation method. The algorithm is shown to provide mesh quality that is competitive with radial basis function based methods, with markedly better performance in preserving boundary layer orthogonality in viscous meshes. The parallelization of the algorithm is described, and the algorithm cost is demonstrated to be O(n log n). The parallel implementation was used to deform meshes of 100 million nodes on nearly 200 processors demonstrating that the method scales to large mesh sizes. Results are provided for a simulation of a high Reynolds number fluid–structure interaction case using this technique.     

Silicon Photonics Rectangular Universal Interferometer

Universal multiport photonic interferometers that can implement any arbitrary unitary transformation between input and output optical modes are essential to support advanced optical functions. Integrated versions of these components can be implemented by means of either a fixed triangular or a fixed rectangular arrangement of the same components. We propose the implementation of a fixed rectangular universal interferometer using a reconfigurable hexagonal waveguide mesh circuit. A suitable adaptation synthesis algorithm tailored to this mesh configuration is provided and the experimental demonstration of a rectangular multiport interferometer by means of a fabricated silicon photonics chip is reported. The 7‐hexagonal cell chip can implement 2 × 2, 3 × 3 and 4 × 4 arbitrary unitary transformations. The proposed hexagonal waveguide mesh operates in a similar way as a Field Programmable Gate Array (FPGA) in electronics. We believe that this work represents an important step‐forward towards fully programmable and integrable multiport interferometers.     

Free Mesh Method: fundamental conception, algorithms and accuracy study

The finite element method (FEM) has been commonly employed in a variety of fields as a computer simulation method to solve such problems as solid, fluid, electro-magnetic phenomena and so on. However, creation of a quality mesh for the problem domain is a prerequisite when using FEM, which becomes a major part of the cost of a simulation. It is natural that the concept of meshless method has evolved. The free mesh method (FMM) is among the typical meshless methods intended for particle-like finite element analysis of problems that are difficult to handle using global mesh generation, especially on parallel processors. FMM is an efficient node-based finite element method that employs a local mesh generation technique and a node-by-node algorithm for the finite element calculations. In this paper, FMM and its variation are reviewed focusing on their fundamental conception, algorithms and accuracy.     

An upgradeable WDM-PON for broadcast and LAN services

We present a novel Wavelength-division-multiplexed passive optical network (WDM-PON) architecture for broadcast and local area network (LAN) services. The virtual ring LAN in the system can be utilized to not only realize LAN services but also provide broadcast services and extra point-to-point (P2P) bandwidth for optical network units (ONUs). A simulation study is performed to demonstrate this scheme. Its result indicates the LAN signals achieve optimum performance when extinction ratio (ER) is 4 dB.     

Parallel adaptation of general three-dimensional hybrid meshes

A new parallel dynamic mesh adaptation and load balancing algorithm for general hybrid grids has been developed. The meshes considered in this work are composed of four kinds of elements; tetrahedra, prisms, hexahedra and pyramids, which poses a challenge to parallel mesh adaptation. Additional complexity imposed by the presence of multiple types of elements affects especially data migration, updates of local data structures and interpartition data structures. Efficient partition of hybrid meshes has been accomplished by transforming them to suitable graphs and using serial graph partitioning algorithms. Communication among processors is based on the faces of the interpartition boundary and the termination detection algorithm of Dijkstra is employed to ensure proper flagging of edges for refinement. An inexpensive dynamic load balancing strategy is introduced to redistribute work load among processors after adaptation. In particular, only the initial coarse mesh, with proper weighting, is balanced which yields savings in computation time and relatively simple implementation of mesh quality preservation rules, while facilitating coarsening of refined elements. Special algorithms are employed for (i) data migration and dynamic updates of the local data structures, (ii) determination of the resulting interpartition boundary and (iii) identification of the communication pattern of processors. Several representative applications are included to evaluate the method.     

A pipelined architecture for real time correction of non-uniformity in infrared focal plane arrays imaging system using multiprocessors

This paper proposes a kind of pipelined electric circuit architecture implemented in FPGA, a very large scale integrated circuit (VLSI), which efficiently deals with the real time non-uniformity correction (NUC) algorithm for infrared focal plane arrays (IRFPA). Dual Nios II soft-core processors and a DSP with a 64+ core together constitute this image system. Each processor undertakes own systematic task, coordinating its work with each other’s. The system on programmable chip (SOPC) in FPGA works steadily under the global clock frequency of 96Mhz. Adequate time allowance makes FPGA perform NUC image pre-processing algorithm with ease, which has offered favorable guarantee for the work of post image processing in DSP. And at the meantime, this paper presents a hardware (HW) and software (SW) co-design in FPGA. Thus, this systematic architecture yields an image processing system with multiprocessor, and a smart solution to the satisfaction with the performance of the system.     

A novel reconfigurable radio-over-fiber system based on flexible optical devices

In this paper, a reconfigurable Radio over Fiber system based on optical switches, optical multimode interference power splitter and tunable optical filters is designed, which can achieve quadrature phase shift keying wireless modulation in optical domain and switch carrier frequency between 30 and 60 GHz. The scheme can make good use of bandwidth resource and realize signal transmission in fiber within 10 km.     

基于混合周期栅网结构的频率选择表面设计研究

在栅网结构上设计的频率选择表面能够同时实现红外高透过率和毫米波带通的物理特性. 为了提高其光学透过率, 降低表面电阻, 抑制高次衍射能量对光学系成像质量的影响, 本文通过分析基于栅网结构的频率选择表面衍射光强和表面电流, 提出一种新型基于混合周期栅网结构的频率选择表面. 计算及实验结果均表明: 在实现稳定的毫米波带通滤波的同时, 基于混合周期栅网结构的频率选择表面红外透过率提高了5%以上, 表面电阻平均降低了4 Ω, 有效地抑制了因高次衍射能量集中分布而对红外光学系统成像质量的影响.     

基于TS201的网络化声纳信号处理平台设计

凭借出色的浮点运算性能,TS201芯片在声纳、雷达等军用电子设备中得到了广泛的应用。然而,由于该芯片本身没有提供原生的高速串口(如串行RapidIO,GbE),不利于多DSP系统接入到网络和实现功能的可重构。本文提出了一种设计方法:利用串行RapidIO技术将TS201芯片构建成可重构的网络,实现了基于TS201芯片信号处理平台的网络化,提高了系统的通用性和使用效率。     

Add/drop applications in fiber ring networks based on a reconfigurable optical add/drop multiplexer in a re-circulating loop

A periodic add/drop system in a fiber ring network was investigated using a reconfigurable optical add/drop multiplexer (ROADM) in a re-circulating fiber loop. After seven cascaded add/drop nodes at every 150 km along the transmission, at bit error ratio (BER) equals to 10⁻⁹ and data rate of 10 Gbps, we observed a 2.5 dB power penalty for the passing through channels with 1050 km transmission distance, and 0.3 dB sensitivity penalty variation for the periodic add/drop channels at every 150 km, respectively.     

基于嵌入式EPICS的合肥光源储存环束流损失监测系统

针对合肥光源储存环恒流运行(Top-off)改造等性能提升的需要,研制了新型的基于嵌入式EPICS架构的储存环束流损失监测(BLM)系统,用于监测储存环中束流损失发生的位置和大小。新BLM处理器获取储存环各处双PIN型光电二极管传感器所采集的簇射电子的信号,分析处理后通过各个处理器内部的嵌入式系统所运行的EPICS程序将数据实时发布到加速器控制网络,使中控室能够实时获取束损的数据。新BLM系统能够实时对双PIN型传感器进行自检操作,排查故障隐患,提高了系统运行的效率和可靠性,经过试运行表明,新BLM系统可完全满足合肥光源恒流的运行需要。     

All optical latches using quantum-dot semiconductor optical amplifier

The design and performance of two optical latches, the Set-Reset (SR) latch and D-Flip-Flop has been studied. These latches are the building blocks of large optical processors. The latches are built using two optical logic operations NAND and NOT. Both NAND and NOT operations are realized by using Mach-Zhender interferometer (MZI) utilizing semiconductor optical amplifier with quantum dot active region (QD-SOA). Nonlinear dynamics including carrier heating and spectral hole-burning in the QD-SOA are taken into account together with the rate equations in order to realize the all-optical logic operations. Results show that this scheme can realize the functions of Set-Reset latch and D-Flip-Flop at high speeds (∼250 Gb/s). The dependence of the output quality (Q factor) on QD-SOA parameters is also discussed.     

Chip-Based Microwave Photonic Payload Repeater for High Throughput Satellites

High-throughput satellite (HTS) is an ideal way to realize cross-regional massive, multifaceted digital exchange services, and it requires a signal processing module that can be massively multiplexed and has high flexibility. Due to the limitations of the frequency characteristics, microwave integrated circuits are difficult to meet this requirement. One solution to this problem is photonic integrated circuits (PICs). However, full-size PIC satellite payloads containing main optoelectronic components are extremely challenging to implement on monolithic or hybrid integrated platforms. Here, the study demonstrates a hybrid integrated on-chip microwave-photonic satellite repeater with large-scale multiplexing potential and high flexibility. This is a demonstration of a hybrid integration of a InP/Si3N4 external cavity laser, arrayed InP modulators, and semiconductor optical amplifiers (SOAs), as well as multifunctional Si3N4 signal processors, to fulfill a 1 × 4 Ka-band repeater module with on-chip arrayed frequency down-conversion and outstanding narrowband photonic channelization. When combined with the full-chip photonic RF repeater, broadband, highly integrated, and cost-effective communications satellite payloads will become realizable more quickly in the near future.     

基于网状光网络的智能实时监测保护系统的研究

目前光网络的拓扑结构越来越复杂,逐渐向网状结构光网络发展。提出了一种新的网状光网络智能实时在线监测保护方案,该方案采用下层嵌入式监测设备＋上层网管中心的模式。在嵌入式监测保护设备上加入保护光纤路由计算的功能,由嵌入式监测保护设备事先用路由算法计算出每条工作光纤的备用光纤路由,在工作光纤发生故障时及时进行切换。该方案实现了真正无人值守的光网络智能实时在线监测保护设备,适应网状光网络的发展要求,实现网状光网络的透明无阻断通信。