Dynamic current testing for CMOS domino circuits

In this paper, we propose a method for testing CMOS domino circuits using the transient power supply current. The method is based on monitoring and processing the transient current. We evaluate the effectiveness of this testing method through simulations of various domino circuits of different sizes. Moreover, we propose a normalising technique to mask the process variations effect associated with current testing. Furthermore, we present a test vector generation algorithm for testing large domino circuits, and develop and implement a clustering technique to improve the fault coverage of the test method when used with large circuits. The clustering algorithm divides the circuit into different clusters where each cluster is fed by a different power supply branch.     

Current testing in dynamic CMOS circuits

Current testing of dynamic CMOS integrated circuits with single phase clock is investigated. The analysis is performed on a single phase stage dynamic module in the presence of internal bridging defects of low resistance. These defects produce intermediate voltage levels which cause difficulties to the logic testing methods based on voltage level comparison. It is shown that current testing may be an effective complement to the usual logic methods. Theoretical bounds on the coverage of single internal bridges obtainable by current testing are given.     

Gate-level power and current simulation of CMOS integrated circuits

In this paper, we present a new gate-level approach to power and current simulation. We propose a symbolic model of complementary metal-oxide-semiconductor (CMOS) gates to capture the dependence of power consumption and current flows on input patterns and fan-in/fan-out conditions. Library elements are characterized and their models are used during event-driven logic simulation to provide power information and construct time-domain current waveforms. We provide both global and local pattern-dependent estimates of power consumption and current peaks (with accuracy of 6 and 10% from SPICE, respectively), while keeping performance comparable with traditional gate-level simulation with unit delay. We use VERILOG-XL as simulation engine to grant compatibility with design tools based on Verilog HDL. A Web-based user interface allows our simulator (PPP) to be accessed through the Internet using a standard web browser     

Dynamic internal testing of CMOS circuits using hot luminescence

Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual devices in CMOS circuits. These pulses are used to directly observe 90 ps gate delays in a ring oscillator as well as the logic switching and gate delays of a counter. By use of a detector with both space- and time-resolution, the dynamics of all the gates of the circuit are simultaneously measured. This noninvasive technique can be extended to smaller device size, as well as probing from the backside of the wafer. The optical emission may provide an alternative to electron beam testing for measuring the dynamics of high-speed CMOS circuits     

Power-constrained testing for bridging and stuck short faults in CMOS combinational circuits

An increasing demand for the portable applications has elevated power consumption to be the most critical parameter. A transistor level model and a testing methodology are presented for detected bridging and stuck short faults in CMOS combinatorial circuits, with the power consumption as a major constraint during testing. The circuits are modeled by the CTF (Current Transfer Function) model. The quiescent current (IDDQ) measurement technique is utilized as the testing methodology. Transistor stuck open faults, that can change the test vector for IDDQ, are incorporated in the model. Simulation using hspice is carried out to support the results.     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

Circuit-level simulation of TDDB failure in digital CMOS circuits

An efficient circuit-level simulator for the prediction of time-dependent dielectric breakdown effects in digital CMOS circuits has been developed and integrated into the reliability simulation tool BERT (Berkeley Reliability Tools). The new module enhances the capability of the earlier SPICE-based oxide breakdown simulator by enabling practical simulations of large digital circuits. We discuss burn-in simulation for digital circuits and show that a significant reduction in oxide breakdown failure probability is possible     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

Switching activity evaluation of CMOS digital circuits using logictiming simulation

The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main source of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE, while Verilog overestimations are up to 68%     

Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits

The possibility to perform realistic fault simulations for Silicon-On-Insulator circuits is investigated. A simple but complete fault simulation model (fsm) for a technology specific effect is described. The effect considered known as kink effect is typical for partially depleted devices but can occur in the presence of a floating body or in the sub-threshold region even in fully depleted devices causing wrong performances. The model proposed here comprises of only a single additional transistor with a controlled body current. It is not a real physical transistor but just one to describe the electrical behaviour of the device when the critical kink-effect situation occurs and for this reason does not increase the simulation time. From the comparison with device characterization measurements on a 1 μm technology device a good matching with the fsm was found.     

Models and Tools for CMOS Integrated Inductors

In this paper we are reporting our research in the development of automatic tools to assist the designers in selecting and automatically laying-out integrated inductors. This task is accomplished by analyzing carefully the lumped equivalent circuit model for these passive components, and using different approaches and modifications depending on the required accuracy and application. As a result modified circuit models for integrated inductors based on the conventional lumped element model are proposed. Model development is based on measurements taken from more than 100 integrated spiral inductors designed and fabricated in a standard silicon process. We show the ability of the proposed models to accurately predict the integrated inductor behavior extending the frequency range where they can be applied as compared with the conventional model.     

Double-edge-triggered D-flip-flops for high-speed CMOS circuits

Two circuits are proposed for double edge-triggered D flip-flops (DETDFFs). A DETDFF responds to both edges of the clock pulse. As compared with positive or negative edge-triggered flip-flops, a DETDFF has advantages in terms of power dissipation and speed. Delay figures for these circuits are measured by simulation. It is shown that these circuits are faster and have lower transistor counts than previously reported circuits. It is shown that these flip-flops can be used at 320-400-MHz clock frequency in a 2-μm technology     

Reverse-voltage protection methods for CMOS circuits

A number of circuit configurations for protection of CMOS circuits against erroneous connections to the surrounding world (e.g. reversal of the supply voltage) are suggested and analyzed. It is found that protection against any permutation of input connections, output connections, and supply voltage connections can be obtained. The design objective is to prevent permanent damage to the chip regardless of how it is connected. It has been found both analytically and experimentally that this design goal can be achieved     

Efficient CMOS counter circuits

Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal     

Dynamic logic CMOS circuits

A structure of dynamic CMOS logic based on the direct interconnection of p-channel logic and n-channel logic dynamic gates is reported. Prevention of glitches and other circuit problems are discussed. Application to a 16-bit parallel-adder design resulted in improved speed as well as important savings in layout area when compared to standard static design.     

RF CMOS body-effect circuits

After a theoretical and analytical study of the body effect in MOS transistors, this paper offers two useful models of this parasitic phenomenon. Thanks to these models, a design methodology, which takes advantage of the bulk terminal, allows to turn this well-known body-effect drawback into an analog advantage, giving thus an efficient alternative to overcome the design constraints of the CMOS VLSI wireless mass market. To illustrate the approach, four RF building blocks are presented. First, a 0.9 V 10 dB gain LNA, covering a frequency range 1.8-2.4 GHz, thanks to a body-effect common mode feedback, is detailed. Secondly, a body-effect linearity controlled pre-power amplifier is presented exhibiting a 5 dB m input compression point (ICP1) variation under 1.8 V power supply for half the current consumption. Lastly, two mixers based on body-effect mixing are presented, which achieve a 10 dB conversion gain under 1.4 V for a −52 dB LO-to-RF isolation. Well suited for low-power/low-voltage applications, these circuits implemented in a 0.18 μm CMOS VLSI technology are dedicated to multi-standard architectures and system-on-chip implementations.     

Low-power interface circuits between adiabatic and standard CMOS circuits

The clocking schemes and signal waveforms of adiabatic circuits are different from those of standard CMOS circuits. This paper investigates the design approaches of low-power interface circuits in terms of energy dissipation. Several low-power interface circuits that convert signals between adiabatic logic and standard CMOS circuits are presented. All interface circuits and their layouts are implemented using TSMC 0.18 μm CMOS technology. The function verifications and energy loss tests for all interfaces are carried out using the net-list extracted from the layout. Full parasitic extraction is done. An adiabatic 8-bit carry look-ahead adder embedded in a static CMOS circuits is used to verify the proposed interfaces. The proposed interface circuits attain large energy savings over a wide range of frequencies, as compared with the previously reported circuits.     

CMOS phase-shifting circuits for wireless beamforming transmitters

Two phase-shifting techniques for wireless beamforming transmitter applications are presented. The first performs quadrant selection using phase-offset local oscillators and fine-grain phase-shifting using RF phase shifters; a 5.2 GHz narrowband phase shifter is designed and fabricated in the CMOS subset of a 0.25 μm SiGe BiCMOS process. Using a tunable all-pass filter topology, it achieves a wide phase-shift range with low loss, and minimizes the number of on-chip passive elements. Measurement results show an insertion loss of 2 dB, an IIP3 of 1 dBm, and a total phase-shift range of 240°; power consumption of the core circuitry is 36.3 mW from a 2.5 V supply. The second approach, a phase-shifting up-converter based on Cartesian combining, achieves a 360° phase shift range that is independent of the operating frequency. Fabricated in 0.18 μm CMOS, it achieves 8 dB conversion gain, 4 dBm OP1 dB, 28 dB sideband rejection, and a 360° phase-shift range at 5.2 GHz without the explicit use of RF phase shifters. The power consumption of its core circuitry is 46.5 mW.