氧化锌锡薄膜晶体管的研究

在ITO玻璃基底上用射频磁控溅射技术生长氧化锌锡(ZnSnO)沟道有源层、用PECVD生长SiO₂薄膜作为薄膜晶体管的栅绝缘层研制了薄膜晶体管(TFT), 器件的场效应迁移率最高达到μ_n=9.1 cm²/(V ·s),阈值电压-2 V,电流开关比为10⁴. 关键词： 氧化锌锡 薄膜晶体管 场效应迁移率     

Effects of annealing process on characteristics of fully transparent zinc tin oxide thin-film transistor

Annealing effect on the performance of fully transparent thin-film transistor （TTFT）, in which zinc tin oxide （ZnSnO） is used as the channel material and SiO2 as the gate insulator, is investigated. The ZnSnO active layer is deposited by radio frequency magnetron sputtering while a SiO2 gate insulator is formed by plasma-enhanced chemical vapor deposition. The saturation field-effect mobility and on/off ratio of the TTFT are improved by low temperature annealing in vacuum. Maximum saturation field-effect mobility and on/off ratio of 56.2 cm2/（V.s） and 3×10^5 are obtained, respectively. The transfer characteristics of the ZnSnO TPT are simulated using an analytical model and good agreement between measured and the calculated transfer characteristics is demonstrated.     

室温生长ZnO薄膜晶体管的紫外响应特性

在室温下采用射频磁控溅射法制备了以ZnO薄膜为沟道层的薄膜晶体管(TFTs).研究表明ZnO薄膜在紫外区具有较高的吸收率,并且ZnO-TFTs对紫外光照射较为敏感.因此,进一步深入研究了ZnO-TFTs紫外光照下的输出和转移特性,结果表明,紫外光照将引起较为明显的光响应电流,且经过光照的器件在光源移除7天后,ZnO沟道层中仍能观察到残余电导现象,其原因可以归结为紫外光辐射在ZnO沟道层中引入了一定数量的氧空位施主态缺陷.     

Review of flexible and transparent thin-film transistors based on zinc oxide and related materials

Flexible and transparent electronics enters into a new era of electronic technologies.Ubiquitous applications involve wearable electronics,biosensors,flexible transparent displays,radio-frequency identifications(RFIDs),etc.Zinc oxide(ZnO) and relevant materials are the most commonly used inorganic semiconductors in flexible and transparent devices,owing to their high electrical performances,together with low processing temperatures and good optical transparencies.In this paper,we review recent advances in flexible and transparent thin-film transistors(TFTs) based on ZnO and relevant materials.After a brief introduction,the main progress of the preparation of each component(substrate,electrodes,channel and dielectrics) is summarized and discussed.Then,the effect of mechanical bending on electrical performance is highlighted.Finally,we suggest the challenges and opportunities in future investigations.     

环形ZnO薄膜谐振器的横模抑制与测试分析

采用Tiersten方程研究了环形ZnO薄膜谐振器中横模寄生问题, 获得了环(圆)形薄膜谐振器的横模振动方程, 求得横模位移场解和频率色散方程; 然后采用电磁学模式合成理论进行分析, 发现环形薄膜谐振器横模频率与环形电极的内外径之比a/b有关, 振动模式可由圆形薄膜谐振器横模模式合成得到, 通过控制a/b能够抑制横模模式数和调控基膜频率. 采用外差激光干涉仪和网络矢量分析仪测量并比较了同批次的圆形和环形薄膜谐振器的上电极横模振动图样和电阻抗曲线. 振动图样显示环形薄膜谐振器振动模式可由半径为a和半径为b的圆形薄膜谐振器振动模式合成, 仅存在节圆数大于0的横模振动, 等于0的横模模式被抑制; 电阻抗曲线显示当a/b为0.436时, 环形薄膜谐振器的基频(约1217 MHz)和圆形的(0, 1)模式频率相等. 测量数据验证了模式合成理论的分析结果正确性, 为薄膜谐振器的横模抑制研究提供了理论基础和新方法.     

SiO2固态电解质中的质子特性对氧化物双电层薄膜晶体管性能的影响

本文采用等离子体增强化学气相沉积技术(PECVD)在室温条件下制备了具有双电层效应的二氧化硅(SiO₂) 固体电解质薄膜, 并以此SiO₂薄膜作为栅介质制备了氧化铟锌(IZO)双电层薄膜晶体管. 本文系统地研究了SiO₂固体电解质中的质子特性对双电层薄膜晶体管性能的影响, 研究结果表明, 经过纯水浸泡的SiO₂固体电解质薄膜可以诱导出较多的可迁移质子, 因此表现出较大的双电层电容. 由于SiO₂固体电解质薄膜具有质子迁移特性, 晶体管的转移特性曲线呈现出逆时针方向的洄滞现象, 并且这一洄滞效应随着栅极电压扫描速率的增加而增大. 进一步对薄膜晶体管的偏压稳定性进行测试, 发现晶体管的阈值电压的变化遵循了拉升指数函数(stretched exponential function)关系.     

Numerical study on the dependence of ZnO thin-film transistor characteristics on grain boundary position

The dependence of transistor characteristics on grain boundary(GB) position in short-channel ZnO thin film transistors(TFTs) has been investigated using two-dimensional numerical simulations.To simulate the device accurately,both tail states and deep-level states are taken into consideration.It is shown that both the transfer and output characteristics of ZnO TFTs change dramatically with varying GB position,which is different from polycrystalline Si(poly-Si) TFTs.By analysing the mechanism of the carrier transportation in the device,it is revealed that the dependence is derived from the degrees of carrier concentration descent and mobility variation with GB position.     

低工作电压聚噻吩薄膜晶体管

以高掺杂Si单晶片作为衬底且充当栅电极,采用磁控溅射法在硅片上沉积HfTiO薄膜作为栅介质层,聚三己基噻吩(P3HT)薄膜作为半导体活性层,金属Au作为源、漏电极,并采用十八烷基三氯硅烷(OTS)对栅介质层表面修饰,在空气环境下成功地制备出聚合物薄膜晶体管(PTFT).PTFT器件测试结果表明,该晶体管在低的驱动电压(<-1 V)下仍呈现出良好的饱和行为,其阈值电压和有效场效应迁移率分别为0.4 V和2.2×10^-2 cm²/V ·s.通过对金属-聚合物-氧化物 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 k栅介质')" href="#">高k栅介质     

溶胶凝胶法制备以HfO2为绝缘层和ZITO为有源层的高迁移率薄膜晶体管

采用溶胶凝胶法制备了h-k氧化铪HfO₂薄膜, 经500℃退火后, 获得了高透过率、表面光滑、低漏电流和相对高介电常数的HfO₂薄膜. 并采用氧化铪作为绝缘层和锌铟锡氧化物作为有源层成功地制备了底栅顶接触结构薄膜晶体管器件. 获得的薄膜晶体管器件的饱和迁移率大于100 cm²·V^-1·s^-1, 阈值电压为-0.5 V, 开关比为5×10⁶, 亚阈值摆幅为105 mV/decade. 表明采用溶胶凝胶制备的薄膜晶体管具备高的迁移率, 其迁移率接近低温多晶硅薄膜晶体管的迁移率.     

Improvement in the electrical performance and bias-stress stability of dual-active-layered silicon zinc oxide/zinc oxide thin-film transistor

Si-doped zinc oxide(SZO) thin films are deposited by using a co-sputtering method,and used as the channel active layers of ZnO-based TFTs with single and dual active layer structures.The effects of silicon content on the optical transmittance of the SZO thin film and electrical properties of the SZO TFT are investigated.Moreover,the electrical performances and bias-stress stabilities of the single- and dual-active-layer TFTs are investigated and compared to reveal the effects of the Si doping and dual-active-layer structure.The average transmittances of all the SZO films are about 90% in the visible light region of 400 nm-800 nm,and the optical band gap of the SZO film gradually increases with increasing Si content.The Si-doping can effectively suppress the grain growth of ZnO,revealed by atomic force microscope analysis.Compared with that of the undoped ZnO TFT,the off-state current of the SZO TFT is reduced by more than two orders of magnitude and it is 1.5 × 10~(-12) A,and thus the on/off current ratio is increased by more than two orders of magnitude.In summary,the SZO/ZnO TFT with dual-active-layer structure exhibits a high on/off current ratio of 4.0 × 10~6 and superior stability under gate-bias and drain-bias stress.     

Photo-induced electrical instability in hydrogenated amorphous silicon based thin-film transistors and the effect of its phase transition

We investigate the origin of photo-induced electrical instability in hydrogenated amorphous silicon based thin-film transistors (a-Si:H TFTs). Photo instability alone was accompanied by a positive shift in the threshold voltage (V_TH) caused by photo irradiation, and even larger positive or negative shift further exacerbated the instability caused by photo-induced electrical bias stress. Such phenomena can occur as a result of extended charge trapping and/or the creation of defect-states at the semiconductor/dielectric interface or in the gate dielectric. The mechanism for such is difficult to describe through chemical interactions of electron-donating and -withdrawing molecules that exhibit a shift in V_TH in only one direction. We also prove that a transition from an amorphous to a protocrystalline phase improves the photo-induced electrical stability. Such results originate from a reduction in the density of the localized states in protocrystalline-Si:H films relative to that of a-Si:H. We believe that this study provides significant information on the device physics of optoelectronics, which commonly exhibit photo-induced instability and charge transport, as a result of prolonged exposure to photo irradiation.     

Characterization of magnesium oxide gate insulators grown using RF sputtering for ZnO thin-film transistors

A ZnO thin-film transistor (TFT) with an MgO insulator was fabricated on a silicon (100) substrate using a radiofrequency magnetron sputtering system. The MgO insulator was deposited using the same deposition system; the total pressure during the deposition process was maintained at 5 mTorr, and the oxygen percentage of O₂/(Ar + O₂) was set at 30%, 50%, or 70%. The process temperature was maintained at below 300 °C. The dielectric constant of the MgO thin layer was approximately 11.35 with an oxygen percentage of 70%. This ZnO TFT displayed enhanced transistor properties, with a field-effect mobility of 0.0235 cm² V⁻¹ s⁻¹, an I_ON/I_OFF ratio of ∼10⁵, and an SS value of 1.18 V decade⁻¹; these properties were superior to those measured for the MgO insulators synthesized using oxygen percentages of 30% and 50%.     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

有机薄膜晶体管驱动聚合物发光二极管研究

研究了有机薄膜晶体管(OTFT)与聚合物发光二极管(PLED)集成制备技术和相关物理问题.OTFT结构为栅极钽(Ta)/绝缘层五氧化二钽(Ta2O5)/有源层并五苯(Pentacene)/源漏极金(Au);PLED器件结构为ITO/PEDOT:PEO(polyethylene oxide)/P-PPV或MEH-PPV/Ba/Al.PEDOT:PEO,P-PPV和MEH-PPV薄膜层均采用丝网印刷技术,实现了OTFT与PLED器件集成发光.其中OTFT器件的阈值电压为-7V,迁移率为0.91cm2/(V.s),并通过OTFT驱动得到以P-PPV和MEH-PPV为发光层的PLED器件的发光亮度分别达到124和26cd/m2,电流效率分别为12.4和1.1cd/A.利用丝网印刷技术可以有效控制高分子薄膜的沉积区域,实现功能器件的集成.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

室温下溅射法制备高迁移率氧化锌薄膜晶体管

为降低氧化锌薄膜晶体管(ZnO TFT)的工作电压,提高迁移率,采用磁控溅射法在氧化铟锡(ITO)导电玻璃基底上室温下依次沉积NbLaO栅介质层和ZnO半导体有源层,制备出ZnO TFT,对器件的电特性进行了表征。该ZnO TFT呈现出优异的器件性能:当栅电压为5 V、漏源电压为10 V时,器件的饱和漏电流高达2.2 m A;有效场效应饱和迁移率高达107 cm~2/(V·s),是目前所报道的室温下溅射法制备ZnO TFT的最高值,亚阈值摆幅为0.28 V/decade,开关电流比大于107。利用原子力显微镜(AFM)对NbLaO和ZnO薄膜的表面形貌进行了分析,分析了器件的低频噪声特性,对器件呈现高迁移率、低亚阈值摆幅以及迟滞现象的机理进行了讨论。     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.