Nanofabrication of tungsten supertip by electron-beam-induced deposition

Two methods were used to fabricate tungsten supertips by electron-beam-induced deposition using 200 keV electrons. The first method is stationary deposition of self-standing tips. The smallest lateral size is less than 10 nm with a rather low aspect ratio of tip. High aspect ratio (up to 30) can only be obtained at a big lateral size with a saturated root diameter of 60–65 nm. The other method is scan deposition of self-supporting tip, with a root width of 7–10 nm and a sharp apex in size of 3 nm. Using this method a higher aspect ratio (more than 72) can be achieved at a smaller lateral size, which is better to fabricate fine supertips for usage.     

薄膜热处理对ZnO薄膜晶体管性能的提高

制备了两种以SiO2为绝缘层的底栅ZnO薄膜晶体管,分别以未退火和退火处理的ZnO薄膜作为有源层.与未退火处理的ZnO薄膜晶体管相比,退火处理的ZnO薄膜晶体管的饱和迁移率由2.3 cm2/(V·s)增大至3.12 cm2/(V·s),阈值电压由20.8V减小至9.9V,亚阈值摆幅由2.6 V/dec减小至1.9 V/...     

Fabrication of 160-nm T-gate metamorphic AlInAs/GaInAs HEMTs on GaAs substrates by metal organic chemical vapour deposition

The fabrication and performance of 160-nm gate-length metamorphic AlInAs/GaInAs high electron mobility tran-sistors (mHEMTs) grown on GaAs substrate by metal organic chemical vapour deposition (MOCVD) are reported. By using a novel combined optical and e-beam photolithography technology, submicron mHEMTs devices have been achieved. The devices exhibit good DC and RF performance. The maximum current density was 817 mA/mm and the maximum transconductance was 828 mS/mm. The non-alloyed Ohmic contact resistance Rc was as low as 0.02 Ω- mm. The unity current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax) were 146 GHz and 189 GHz, respectively. This device has the highest fT yet reported for a 160-nm gate-length HEMTs grown by MOCVD. The output conductance is 28.9 mS/mm, which results in a large voltage gain of 28.6. Also, an input capacitance to gate-drain feedback capacitance ratio, Cgs/Cgd, of 4.3 is obtained in the device.     

Dependence on substrate topography of growth of nanosized dendritic structures in an electron-beam-induced deposition process

Nanometer-sized W-dendrites are fabricated on Al₂O₃ substrates with an electron-beam-induced deposition process. Dependence of growth of nanodendrite on surface topography is investigated with transmission electron microscopy. It is confirmed that the nanodendrite grows on convex surfaces but not around a hole on a substrate. These are attributed to different distribution of charges on surfaces with different topographies during electron beam irradiation when charges are produced on the surface due to emission of second electrons. The charges accumulate on convex surface and do not distribute around a hole. Therefore, the nanodendrite grows on the former and not on the latter.     

Synthesis of GaN nanowires on gold-coated SiC substrates by novel pulsed electron deposition technique

A two-step approach for macro-synthesis of GaN nanowires was developed in this study. GaN nanoparticles were firstly synthesized through a facile solid-state reaction using an organic reagent dicyandiamide (C₂N₄H₄) and Ga₂O₃ as precursors. Subsequently, single-crystalline wurtzite GaN nanowires were grown on gold-coated 6H-SiC substrates via novel pulsed electron deposition (PED) technique using the as-prepared GaN nanoparticles as target, which provides a new route employing nanoparticles as precursors to fabricate GaN nanowires. It is found that pulsed electron ablation induced Ga and N plasma directly towards the gold-coated substrate to initialize the vapor-liquid-solid (VLS) growth processes. The morphological and structural properties were investigated in detail and Raman scattering spectrum of these nanowires presented some new features.     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

AlGaN/GaN 高电子迁移率晶体管漏电流退化机理研究

本文首先制备了与AlGaN/GaN高电子迁移率晶体管 (HEMT) 结构与特性等效的AlGaN/GaN异质结肖特基二极管, 采用步进应力测试比较了不同栅压下器件漏电流的变化情况, 然后基于电流-电压和电容-电压测试验证了退化前后漏电流的传输机理, 并使用失效分析技术光发射显微镜 (EMMI) 观测器件表面的光发射, 研究了漏电流的时间依赖退化机理. 实验结果表明: 在栅压高于某临界值后, 器件漏电流随时间开始增加, 同时伴有较大的噪声. 将极化电场引入电流与电场的依赖关系后, 器件退化前后的 log(I_FT/E)与√E 都遵循良好的线性关系, 表明漏电流均由电子Frenkel-Poole (FP) 发射主导. 退化后 log(I_FT/E)与√E 曲线斜率的减小, 以及利用EMMI在栅边缘直接观察到了与缺陷存在对应关系的“热点”, 证明了漏电流退化的机理是: 高电场在AlGaN层中诱发了新的缺陷, 而缺陷密度的增加导致了FP发射电流I_FT的增加. 关键词： AlGaN/GaN 高电子迁移率晶体管 漏电流 退化机理     

Structural and electrical characterization of annealed Si1-xCx/SiC thin film prepared by magnetron sputtering

Si-rich Sil-xCx/SiC multilayer thin films are prepared using magnetron sputtering, subsequently followed by thermal annealing in the range of 800-1200 ℃. The influences of annealing temperature （Ta） on the formation of Si and/or SiC nanocrystals （NCs） and on the electrical characteristics of the multilayer film are investigated by using a variety of analytical techniques, including X-ray diffraction （XRD）, Raman spectroscopy and Fourier transform infrared spectrometry （FT-IR）, current-voltage （I-V） technique, and capacitance-voltage （C-V） technique. XRD and Raman analyses indicate that Si NCs begin to form in samples for Ta _ 800 ~C. At annealing temperatures of 1000 ℃ or higher, the formation of Si NCs is accompanied by the formation of SiC NCs. With the increase in the annealing temperature, the shift of FT-IR Si-C bond absorption spectra toward a higher wave number along with the change of band shape can be explained by a Si-C transitional phase between the loss of substitutional carbon and the formation of SiC precipitates and a precursor for the growth of SiC crystalline. The C-V and I-V results indicate that the interface quality of Si1-xCx/SiC multilayer film is improved significantly and the leakage current is reduced rapidly for Ta ≥ 1000 ℃, which can be ascribed to the formation of Si and SiC NCs.     

基于原位等离子体氮化及低压化学气相沉积-Si_3N_4栅介质的高性能AlGaN/GaN MIS-HEMTs器件的研究

通过对低压化学气相沉积(LPCVD)系统进行改造,实现在沉积Si_3N_4薄膜前的原位等离子体氮化处理,氮等离子体可以有效地降低器件界面处的氧含量和悬挂键,从而获得了较低的LPCVD-Si_3N_4/GaN界面态,通过这种技术制作的MIS-HEMTs器件,在扫描栅压范围V_(G-sweep)=(-30 V,+24 V)时,阈值回滞为186 mV,据我们所知为目前高扫描栅压V_(G+)(20 V)下的最好结果.动态测试表明,在400 V关态应力下,器件的导通电阻仅仅上升1.36倍(关态到开态的时间间隔为100μs).     

Effect of accelerating voltage on crystallization of self-standing W-nanodendrites fabricated on SiO2 substrate with electron-beam-induced deposition

Self-standing W-nanodendrite structures were grown on SiO₂ substrate using an electron-beam-induced deposition (EBID) process with various accelerating voltages from 400 to 1000 kV. Effect of accelerating voltage on crystallization of the nanodendrites was investigated. The nanodendrites consisted of nano-sized grains and amorphous structures. The nano-sized grains were determined to be W crystal in BCC structure. The higher was electron beam accelerating voltage, the higher was crystallinity of the as-fabricated nanodendrites. It is suggested that high-energy electron irradiation enhances diffusion of W atoms in the nanodendrites, promotes crystallization of W grains.     

衬底对化学气相沉积法制备氧化硅纳米线的影响

通过化学气相沉积法在不同衬底上制备了大量的氧化硅纳米线.选用衬底为Si片、带有约100nm厚SiO2氧化层Si片和石英片.利用场发射扫描电子显微镜(SEM)和透射电镜(TEM，配备有能谱仪)对样品的表面形貌、结构和成分进行研究.结果表明：这些纳米线都为非晶态，但在不同衬底上生长的纳米线形貌、尺寸和化学成分不同.讨论了各种衬底对不同特征氧化硅纳米线生长的影响. 关键词： 化学气相沉积 纳米线 纳米颗粒     

Catalyst-free growth of well-aligned arsenic-doped ZnO nanowires by chemical vapor deposition method

ZnO nanowires with different arsenic concentration were grown on Si (1 0 0) substrates by chemical vapor deposition method without using catalyst. Zn/GaAs mixed powders were used as Zn and As source, respectively. Oxygen was used as oxidant. The images of scanning electron microscope show that the arsenic-doped ZnO nanowires with preferred c-axial orientation were obtained, which is in well accordance with the X-ray diffraction analysis. The arsenic related acceptor emission was observed in the photoluminescence spectra at 11 K for all arsenic-doped ZnO samples. This method for the preparation of arsenic-doped ZnO nanowires may open the way to realize the ZnO nanowires based light-emitting diode and laser diode.     

多层Ti/Al电极结构对Ga N/AlGaN HEMT欧姆接触特性的影响

研究了多层Ti/Al结构电极对GaN/AlGaN HEMT欧姆接触特性及表面形态的影响。采用传输线模型对各结构电极的比接触电阻率进行了测量,采用扫描电子显微镜对电极表面形态进行扫描。实验结果显示,在同样的退火条件下,随着Ti/Al层数的增加,比接触电阻率逐渐减小,表面形态趋于光滑;降低Ti/Al层的厚度会加剧Au向内扩散而增加比接触电阻率,但能稍微改善表面形态;Ti比例过高会影响Ti N的形成导致比接触电阻率增加,但能明显改善表面形态。     

Electrical transport properties of graphene-covered-Cu wires grown by chemical vapor deposition

We investigated the field-effect transistor (FET) characteristics of 15-μm graphene-covered copper wires (G-wires). Unlike the previously reported graphene FET, carries initially showed p-type like FET characteristics in two-terminal transport measurements. Our results indicate that the electrical transport processes in a G-wire FET occur in both the heavily p-doped contact and the p-doped radial graphene channel, as a p-channel. The interfacial potential barrier between the contact electrode and the radial graphene channel is small, but there is a radial potential barrier that limits electrical transport through the copper core in chemical vapor deposition (CVD) grown samples. The p-type FET characteristics appeared clearly after the oxidation of the G-wires.     

Evolution of self-assembled Ge/Si island grown by ion beam sputtering deposition

The effect of temperature and Ge coverage on the evolution of self-assembled Ge/Si islands grown by ion beam sputtering deposition is studied. Atomic force microscopy and Raman spectroscopy are used to analyze the island morphology and the intermixing between Si and Ge. The experiments are presented in two aspects. First, when the temperature is increased, intermixing is promoted, resulting in the reappearance of low aspect ratio islands. Second, a different evolution pathway is observed, in which short islands initially don’t grow along the constant ratio of 11:1 (diameter:height) and the islands always grow faster in vertical direction. In summary, the interdiffusion, surface diffusion, and amount of Ge determines the evolution of Ge/Si islands.     

Well-aligned ZnO nanowires grown on Si substrate via metal–organic chemical vapor deposition

ZnO nanowires were grown on silicon substrate by metal–organic chemical vapor deposition (MOCVD) without catalysts. The scanning electron microscopy (SEM) observations along with X-ray diffraction (XRD) results suggest that the ZnO nanowires are single crystals vertically well-aligned to silicon substrate. Room-temperature photoluminescence (PL) measurement reveals strong UV emission and weak green emission, which demonstrates that the nanowires are of good optical properties. The mechanism of the catalyst-free growth of ZnO nanowires on silicon substrate is proposed.     

Electroless deposition of Sno2 and antimony doped SnO2 films

Thin polycrystalline films of SnO₂ and antimony doped SnO₂ have been prepared by simple economic electroless deposition technique. The transmittance in the visible range and the reflectance in the i.r. range for SnO₂ films are ～80% and ～70%, respectively, with resistivity ～10^?2 Ω cm. On the other hand, antimony doped SnO₂ films have transmittance in the visible range and reflectance in the i.r. range, as good as ～86% and ～83%, respectively, with resistivity as low as ～10^?3Ω cm. By vacuum annealing, the resistivity of both types of films has been brought down as low as ～10^?3 and ～10^?4 Ω cm, respectively.     

不同入射角度下强流脉冲电子束能量沉积剖面和束流传输系数模拟计算

 强流脉冲电子束在材料中的能量沉积剖面、能量沉积系数和束流传输系数受其入射角的影响很大，理论计算了0.5~2.0MeV的电子束以不同的入射角在Al材料中的能量沉积剖面和能量沉积系数，并且还计算了0.4~1.4MeV电子束以不同入射角穿透不同厚度C靶的束流传输系数。计算结果表明，随着入射角的增大，靶材表面层单位质量中沉积的能量增大，电子在靶材料中穿透深度减小，能量沉积系数减小，相应的束流传输系数也减小；能量为0.5~2.0MeV的电子束当入射角在60°~70°时在材料表面层单位质量中沉积的能量较大。     

Characteristics and properties of metal aluminum thin films prepared by electron cyclotron resonance plasma-assisted atomic layer deposition technology

Metal aluminum (Al) thin films are prepared by 2450 MHz electron cyclotron resonance plasma-assisted atomic layer deposition on glass and p-Si substrates using trimethylaluminum as the precursor and hydrogen as the reductive gas. We focus our attention on the plasma source for the thin-film preparation and annealing of the as-deposited films relative to the surface square resistivity. The square resistivity of as-deposited Al films is greatly reduced after annealing and almost reaches the value of bulk metal. Through chemical and structural analysis, we conclude that the square resistivity is determined by neither the contaminant concentration nor the surface morphology, but by both the crystallinity and crystal size in this process.     

Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxynitride (HfSiON) on ultrathin SiO₂ buffer layer. The gate dielectric with 10? (1?= 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielectric constant (k=14) and low gate-leakage current (I_g=1.9×10^-3A/cm² @V_g=V_fb-1V for EOT of 10?). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.