Improved Biquad Structures Using Double-Output Transconductance Blocks for Tunable Continuous-Time Filters

A family of g_m-C biquad structures is derived. These biquads require only a pair of grounded capacitors and three transconductors. It is shown that a pair of complex zeros can be realized simply by replicating the output stage of the transconductance block, thereby constructing a second output current that is proportional to the original output current. Although these biquad structures are very compact, they allow independent programming of the filter's center frequency andQ . IC simulations and measurements are presented using a fifth-order tunable filter as an example.     

Sinh-domain complex integrators

The basic building blocks for performing complex signal processing in the Sinh-domain are introduced in this article. Attractive offered benefits are the capabilities for achieving resistorless realisations with electronic adjustment of their frequency characteristics, independent tuning of centre frequency and bandwidth and operating in a low-voltage environment. In addition, the inherent class-AB operation of Sinh-domain filters allows the handling of signals greater than the bias current, leading to a power saving. The aforementioned benefits have been evaluated through simulation results, using the Analog Design Environment of the Cadence software.     

Realization of Series and Parallel R-L and C-D Impedances Using Single Differential Voltage Current Conveyor

In this paper, realization of series and parallel R-L immitances using differential voltage current conveyor (DVCC) is presented. The proposed circuits enable actively simulation series and parallel R-L and (-R)-(-L) immitances. Applying RC:CR transformation to the proposed configurations, series and parallel C-D and (-C)-(-D) simulators can also be realized with the same topology. They employ single DVCC and at most three resistors and one capacitor. No component matching constraints are imposed for the realisations. The performance of the proposed immittance simulators is demonstrated on both a second-order voltage and second-order current-mode filters. PSPICE simulations are given to verify the theoretical analysis. An erratum to this article is available at .     

A Continuous Time Auto-Zero Offset Compensated Switched Capacitor Integrator

A continous mode CMOS switched capacitor integrator with almost zero offset is presented. The offset is compensated using an auto-zero technique and proper circut elements have been used to attenuate disturbances due to charge injection and clock feedthrough. The circuit includes two parallel paths which operate alternately in order to integrate in one path while compensating the offset in the other path. The circuit is capable of removing the offset voltage and its integral, and many other spurious signals at the output. The designed integrator has an initial offset of about –250 V which raises to an amount of about –400 V after one second of integration.     

Low Power Programmable Current Mode Circuits

In this article (based on transconductance adjustment) novel low power, programmable circuits such as switched transconductance and neuron structures that set foundations for low power VLSI sampled data filtering circuits and neural networks are proposed. The switched transconductance integrator structures are presented and their performances are compared to switched current counterparts. Also the analog circuits for activation function and programmable weight synaptic connections are presented and discussed. A qualitative comparison is made between standard and proposed circuits.     

Generalised Christoffel–Darboux formula most directly applied in generating fully symmetric doubly resistively terminated LC lossless ladder filters

In this article, the approximation problem of a continuous analogue filter function of even and odd order is solved mathematically most directly applying the proposed generalised Christoffel–Darboux formula for two continuous orthogonal polynomials (Chebyshev first and second kind) on the equal finite segment of orthogonality in a compact explicit representative form. A set of analytic expressions of the proposed formula for the representative examples of odd-orders is given. Additionally, these expressions are applied in generating new excellent class all pole low-pass prototype analogue filter functions of odd orders (7, 9, 11, and 13th order). Based on the generated functions, the fully symmetric doubly resistively terminated LC ladder filter networks are realised by Darlington realisation. The generated filters are analysed, and their characteristics are presented. The effects of finite tolerance of a critical reactance of these ladder filters on the filter characteristics are considered. The filters generated by the proposed formula show excellent properties and possess important advantages in comparison to the corresponding filters generated by other methods.     

单一单位增益放大器的Q增强SC滤波器

本文阐述了采用单位增益放大器的SC滤波器的设计方法。基于无源Q增强技术,由Sallew Key有源RC电路导出了一系列Q增强的二阶SC低通、高通和带通滤波器。设计表明,本文提出的Q增强SC电路比文献给出的电路需要小得多的电容分散度。本文考察了这些电路灵敏度和有限GB对SC电路的影响。用分立元件做了实验,实验结果与理论计算相吻合。     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

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Single MIMO-OTA and single-grounded-capacitor-based first-order allpass filter design

A novel first-order voltage-mode allpass (AP) filter employing a single multiple-input-multiple-output operational-transconductance-amplifier (MIMO-OTA) and a single grounded capacitor is introduced in this article. Compared to the corresponding already published topologies, the offered benefits are as follows: it employs minimum number of active and passive components; the only capacitor is grounded, which is good for a monolithic integration of an IC; and the absence of any matching condition for its realisability. The performance of the proposed circuit has been evaluated through simulation results, utilising the analogue design environment of Cadence software.     

基于可编程模拟器件的信号发生器

介绍了TRAC完全可重配置模拟器件和及其开发应用软件，并以此为基础设计了信号发生器，给出了设计图纸和仿真结果，该信号发生器性能稳定，不需要调试。     

用于RDS信号处理的开关电容滤波器的设计

RDS是对FM广播系统应用的重大发展,其接收和解码需要性能较高的开关电容滤波器。通常采用计算z域传递函数,并将其分级用开关电容电路实现的设计方法。这种方法计算复杂,且滤波器的各级结构差异较大。文中提出一种基于重复单元的设计思路,将一个高阶开关电容滤波器拆分为几个结构完全一样的低阶滤波器单元。以二阶连续时间滤波器为基础,用开关电容模拟等效电阻,最终完成一个用于RDS信号处理的八阶开关电容滤波器,简化了设计,但同样具有较好的性能。     

Printed Organic One‐Time Programmable ROM Array Using Anti‐fuse Capacitor

This paper proposes printed organic one‐time programmable read‐only memory (PROM). The organic PROM cell consists of a capacitor and an organic p‐type metal‐oxide semiconductor (PMOS) transistor. Initially, all organic PROM cells with unbroken capacitors store “0.” Some organic PROM cells are programmed to “1” by electrically breaking each capacitor with a high voltage. After the capacitor breaking, the current flowing through the PROM cell significantly increases. The memory data is read out by sensing the current in the PROM cell. 16‐bit organic PROM cell arrays are fabricated with the printed organic PMOS transistor and capacitor process. The organic PROM cells are programmed with –50 V, and they are read out with –20 V. The area of the 16‐bit organic PROM array is 70.6 mm².     

CMOS四路可加权高频模拟开关的设计和研究

介绍了一种可对高频信号进行取样、加权、控制、叠加的模拟信号处理开关集成电路,通过两个高宽长比的高跨导NM O S晶体管可实现权值的粗调和微调。该电路采用标准0.6μm CM O S工艺制造。测试结果表明:该电路的工作频段为50~250 MH z时,导通时最小插入损耗约为-5.0~-10.5 dB,关断时隔离度可达-40.5~-23.4 dB左右;其连续可调的加权动态范围最大值为21.3 dB。     

A Novel Log-Domain Differentiator

A log-domain differentiator circuit, constructed using an appropriate input stage and a multiplier block, is proposed in this Letter. The input stage compresses the voltage at the capacitor's nodes and simultaneously produces a replica of the current that flows through the capacitor. The multiplier block realizes the desired output current. The analysis of the proposed circuit has been verified through simulation results.     

面向多功能模拟信号处理的开关电流型可重构模拟电路研究

现有的离散时间型可重构模拟电路采用开关电容技术,存在功能有限、带宽低、与数字CMOS工艺不兼容等问题.本文提出了一种基于电流模取样数据技术的可重构模拟电路,能够与数字CMOS工艺技术兼容.设计了细粒度开关电流型可重构模拟单元,设计了面向开关电流型CAB互连的可编程网络结构.在4×2规模的可重构模拟阵列上,重构实现了三个...     

Explicit form of new class of extremal filter functions with mini-max behaviour of summed sensitivity function

In this article, the all-pole low-pass filter function with mini-max for the summed sensitivity function in the pass-band is considered. With the application of Chebyshev polynomials of the first kind, the proposed filter function is obtained in an explicit form with a maximum number of oscillations of the summed sensitivity function in the pass-band. The calculation of the filter function is derived by using the summed sensitivity function as a starting point. New original approximation function is derived in order to achieve a mini-max summed sensitivity function in the filter pass-band. Sensitivity analysis is carried out and a comparison of the summed sensitivity and the group delay of the proposed and classical all-pole filters is given. Minimisation of the summed sensitivity function is important for reduction of the deviation of the magnitude response caused by temperature changes of the continuous-time active filters implemented into the analogue front end or as programmable chips.     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

可编程细胞神经网络硬件实现及应用研究

 本文提出一种模板可编程细胞神经网络的硬件实现方法,设计构成CNN的细胞体电路、A模板电路和B模板电路,组成CNN并进行在图像处理中的应用研究.仿真结果表明,所设计的硬件电路具有结构简单、功耗低、频率特性好、模板参数可编程等特点,可以方便地构成各种规模的CNN,在图像处理应用中具有一定的灵活性和通用性.     

New CFOA-based floating immittance emulators

This paper presents four new topologies for emulating floating immittance functions. Each circuit uses two or three current-feedback operational-amplifiers (CFOAs) and three passive elements. The proposed topologies can emulate positive/negative lossless and lossy floating inductances, and positive/negative capacitance, resistance and inductance multipliers in addition to floating frequency-dependent positive and negative resistances. The functionality of the proposed circuits is verified using the Advanced Design System software and the AD844 CFOA. The simulation results are in excellent agreement with the theoretical calculations.     

Analog VLSI Design Constraints of Programmable Cellular Neural Networks

Analog parallel signal processing systems, like cellular neural networks (CNN's), intrinsically have a high potential for perception-like signal processing tasks. The robust design of analog VLSI requires a good understanding of the capabilities as well as the limitations of analog signal processing. Implementation-oriented theoretical methods are described to compute the effect of all types circuit non-idealities with random or systematic causes on the static and dynamical behavior of CNN's and to derive specifications for the cell circuit building blocks. The fundamental impact of transistor mismatch on the trade-off between the speed, accuracy and power performance of CNN chips is demonstrated. A design methodology taking into account the effect of transistor mismatch is proposed and experimental results of a CNN chip implementation designed with this method are discussed.