Rapid Chip设计平台快速设计系统级芯片

引言 Rapidchip Platform ASIC基本上是在一个芯片(SoC)上快速设计系统而提供的新方法.这些耐用的PlatformASIC填补了FPGA和标准单元ASIC之间的空隙,并组合了两者最好的特性.RapidchipPlatform ASIC探讨交付包含复杂的嵌入式IP的高性能和高密度的解决方案;并且它们比标准单元ASIC要少一半的设计时间,开发成本是几分之一.     

系统级封装技术及其应用

本文介绍了系统级封装技术及其兴起背景,对比了与SoC的异同。通过分析系统级封装的技术特点,阐述了其优势;分析了系统级封装的成本构成和特点。本文从集成电路产业链整合的观点,分析了国内系统级封装的机遇与挑战;以长电科技为例,介绍了系统级封装在设计、制造上的关键技术与当前的能力,并分析了未来的趋势和挑战。本丈还对当前的系统级封装产品与应用领域做了详细介绍。     

片上系统时代呼唤新设计方法

越来越多的复杂IC是用深亚微米技术的片上系统(SOC)技术制造的。事实上，SOC是利用深亚微米技术的唯一有效途径(也是半导体厂商收回建厂投资的唯一有效途径)。虽然如此，还是有一些问题应当考虑：     

系统级封装设计套件实现系统级IC与封装的协同设计

系统级封装设计套件包括Cadence Radio Frequency SiP Methodology Kit、两款新的RFSiP产品（Cadence SiP RF架构和Cadence SiP RF版图）以及三款新的数字SiP产品（Cadence SiP数字架构，Cadence SiP数字信号完整和Cadence SiP数字版图）。     

电动汽车的系统级EMC设计

在分析整车EMC设计现状的基础上,以大量部件和整车的设计、测试经验为支撑,借鉴学习国外一些车型的先进设计思路,从EMC工程设计角度,提出了一种电动汽车系统级EMC开发方法.该方法成功应用于各研发车型,改变了以往样车难以顺利通过EMC法规的局面,同时保证了系统内EMC.     

专用指令集处理器系统级设计方法

以专用指令集处理器（ASIP）为核心的SoC系统是基于特定应用，设计嵌入式处理器的一个重要发展方向。给出了一种高效的系统级指令集模型设计空间搜索和体系结构仿真的方法。该方法可以在设计的早期阶段对软件和硬件进行协同设计和仿真，针对应用优化系统性能。利用该方法成功设计的ASIP系统，完成基4-64点DIF FFT需要310个时钟周期。     

射频系统的系统级封装

论述了高速数据处理和高密度封装技术的特点及对射频系统封装的特殊要求,介绍了射频系统封装的基本技术和一种包含LNA、PPA、滤波器及天线开关的射频系统级封装模块.概述了射频系统级封装的设计、仿真和测试的方法和步骤.     

Cadence最新套件推动系统级封装设计主流化

近日．Cadence设计系统有限公司宣布推出业界第一套完整的能够推动SiPIC设计主流化的EDA产品。Cadence解决方案针对目前SiP设计中依赖“专家工程”方式存在的固有局限性．提供了一套自动化、整合的、可信赖并可反复采用的工艺以满足无线和消费产品不断提升的需求。这套新产品包括Cadence Radio Frequency SiP Methodology Kit、两款新的RF SiP产品（Cadence SiP RF架构和Cadence SiP RF版图）以及3款新的数字SiP产品（Cadence SiP数字架构、Cadence SiP数字信号完整和Cadence SiP数字版图）。     

Complexity management in system-level design

The system-level design problem spans a large design space. Typically, the designer needs to explore possible target architectures, experiment with different tools, and work with a range of constrains and optimization criteria. This design process is quite complex and involves considerable bookkeeping and management, in addition to sophisticated design tools. We believe that managing the design process is an important (although often neglected) part of system-level design. The contribution of this paper is in two parts. First, we present a framework for systematically managing the design process. Secondly, we illustrate how this framework can be used to manage a system-level design environment that consists of a suite of sophisticated hardware and software design tools.We begin by identifying some of the desirable features of system-level design methodology management. A candidate framework that manifests these features is presented. Complex design flows with iterative and conditional behavior can be specified within the framework. The framework also supports automated scheduling of tools in a well-defined design flow. It has been implemented as the DMM domain in Ptolemy.In the second part of the paper, we describe a case study that we have developed within this framework. The case study, called the Design Assistant, is a complete hardware-software codesign environment. It encapsulates various codesign tools for specification, partitioning, and synthesis; their interplay can be managed efficiently by the design methodology management framework.     

Discrete-time battery models for system-level low-power design

For portable applications, long battery lifetime is the ultimate design goal. Therefore, the availability of battery and voltage converter models providing accurate estimates of battery lifetime is key for system-level low-power design frameworks. In this paper, we introduce a discrete-time model for the complete power supply subsystem that closely approximates the behavior of its circuit-level continuous-time counterpart. The model is abstract and efficient enough to enable event-driven simulation of digital systems described at a very high level of abstraction and that includes, among their components, also the power supply. The model gives the designer the possibility of estimating battery lifetime during system-level design exploration, as shown by the results we have collected on meaningful case studies. In addition, it is flexible and it can thus be employed for different battery chemistries     

A methodology and design tools to support system-level VLSI design

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraint-driven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology     

Symbolic system-level design methodology for multi-mode reconfigurable systems

Modern embedded systems provide a variety of functionality as operational modes, each corresponding to a mutually exclusive phase of operation. This paper provides a system level design methodology tailored for such multi-mode systems. By incorporating knowledge about the temporal behavior, it is possible to share hardware by means of partial reconfiguration on sophisticated Field Programmable Gate Arrays (FPGAs), and thus, reduce costs and improve performance. The presented methodology is based on an exploration model, which specifies the temporal behavior of the system functionality as well as the architectural characteristics of nowadays reconfigurable technology. We develop a symbolic encoding of this system specification, which enables unified system synthesis by applying sophisticated optimization techniques to perform allocation, binding, placement of partially reconfigurable modules, and routing the on-chip communication. The presented system-level design methodology complies with the state-of-the-art synthesis tools and communication technologies for partially reconfigurable systems. We demonstrate this by experiments on test cases from the image processing domain applying state-of-the-art technology. The results give evidence of the efficiency of the methodology and show the superiority in terms of runtime and quality of the found solutions compared to existing system-level synthesis approaches.     

A system-level bandwidth design method for wormhole network-on-chip

To improve the Network-on-Chip (NoC) performance, we propose a system-level bandwidth design method customising the bandwidths of the NoC links. In details, we first built a mathematical model to catch the relationship between the NoC commutation latency and the NoC link bandwidth, and then develop a bandwidth allocation algorithm to automatically optimise the bandwidth for each NoC link. The experimental results show that our bandwidth-customising method improves the NoC performance compared to the traditional uniform bandwidth allocation method. Besides, it can also make our NoC to achieve the same communication performance level as the uniform bandwidth NoC but using fewer bandwidth resources, which is beneficial to save the NoC area and power.     

A survey of design techniques for system-level dynamic powermanagement

Dynamic power management (DPM) is a design methodology for dynamically reconfiguring systems to provide the requested services and performance levels with a minimum number of active components or a minimum load on such components. DPM encompasses a set of techniques that achieves energy-efficient computation by selectively turning off (or reducing the performance of) system components when they are idle (or partially unexploited). In this paper, we survey several approaches to system-level dynamic power management. We first describe how systems employ power-manageable components and how the use of dynamic reconfiguration can impact the overall power consumption. We then analyze DPM implementation issues in electronic systems, and we survey recent initiatives in standardizing the hardware/software interface to enable software-controlled power management of hardware components     

Issues for low-power CAD tools: A system-level design study

A case study in low-power system-level design is presented. We detail the design of a low-power embedded system, a touchscreen interface device for a personal computer. This device is designed to operate on excess power provided by unused RS232 communication lines. We focus on the design and measurement procedures used to reduce the power requirements of this system to less than 50 mW. Additionally, we highlight opportunities to use system-level design and analysis tools for low-power design and the obstacles that prevented using such tools in this design.