1.55μmSi_(1-x)Ge_x光波导与Si_(1-x)Ge_x/Si多量子阱探测器集成的优化设计

对１．５５μｍ波长的Ｓｉ１－ｘＧｅｘ光波导和Ｓｉ１－ｘＧｅｘ／Ｓｉ多量子阱（ＭＱＷ）红外探测器的集成器件结构进行了系统的分析和优化设计。优化结果为：１）对Ｓｉ１－ｘＧｅｘ光波导，Ｇｅ含量ｘ＝０．０５，脊宽、高和腐蚀深度分别为８、３和２．６μｍ；２）对Ｓｉ１－ｘＧｅｘ／Ｓｉ多量子阱红外探测器，Ｇｅ含量ｘ＝０．５，探测器由厚度为５５０ｎｍ、２３个周期的６ｎｍＳｉ０．５Ｇｅ０．５＋１７ｎｍＳｉ组成，长度约２ｍｍ。结果表明，这种结构器件的内量子效率可达８８％。     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO7340Q, 7325http://cpb.iphy.ac.cn/CN/10.1088/1674-1056/19/5/057302https://cpb.iphy.ac.cn/CN/article/downloadArticleFile.do?attachType=PDF&id=111774Ge substrate, transistor, HfSiON, hole mobilityProject supported by the National Basic Research Program of China (Grant No.~2006CB302704).Ge and Si p-channel metal--oxide--semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance--voltage curve hysteresis of Ge metal--oxide--semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO$_{x}$ ($1Ge;substrate;transistor;HfSiON;hole;mobilityGe and Si p-channel metal-oxide-semiconductor field-effect-transistors(p-MOSFETs) with hafnium silicon oxynitride(HfSiON) gate dielectric and tantalum nitride(TaN) metal gate are fabricated.Self-isolated ring-type transistor structures with two masks are employed.W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately.Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor(MOS) capacitors may be caused by charge trapping centres in GeOx(1 < x < 2).Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method.The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V.s) and 81.0 cm2/(V.s),respectively.Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.     

Ge self-diffusion in epitaxial Si(1)-(x)Ge(x) layers

Diffusion coefficients and activation energies have been determined for Ge diffusion in strain-relaxed Si(1)-(x)Ge(x) with x = 0.00, 0.10, 0.20, 0.30, 0.40, and 0.50. The activation energy drops from 4.7 eV in Si and Si(0.90)Ge(0.10) to 3.2 eV at x = 0.50. This value compares with the literature value for Ge self-diffusion in Ge, suggesting Ge-like diffusion already at x approximately equal to 0.5. The effect of strain on the diffusion was also studied showing a decrease in diffusion coefficient and an increase in activation energy upon going from compressive over relaxed to tensile strain.     

Majority carrier transistor based on voltage-controlled thermionic emission

A new type of transistor is proposed based on gate-controlled charge injection in unipolar semiconductor structures. Its design has some similarity with the recently fabricated triangular barrier diodes but contains an additional input circuit which allows an independent control of the barrier height for thermionic emission. This circuit is provided by a MOS gate on the semiconductor surface. In the proposed device the current flows perpendicular to the semiconductor surface over a planar potential barrier controlled by the gate. The static transconductance characteristics and dynamical response are analyzed. The characteristic response time is limited by the time of flight of electrons across the structure and can be in the picosecond range. The gate voltage required to switch the output current at room temperature is of order 0.2 V.     

光器件应用改性Ge的能带结构模型

Ge为间接带隙半导体,通过改性技术可以转换为准直接或者直接带隙半导体.准/直接带隙改性Ge半导体载流子辐射复合效率高,应用于光器件发光效率高;同时,准/直接带隙改性Ge半导体载流子迁移率显著高于Si半导体载流子迁移率,应用于电子器件工作速度快、频率特性好.综合以上原因,准/直接带隙改性Ge具备了单片同层光电集成的应用潜力.能带结构是准/直接带隙改性Ge材料实现单片同层光电集成的理论基础之一,目前该方面的工作仍存在不足.针对该问题,本文主要开展了以下三方面工作:1)揭示了不同改性条件下Ge材料带隙类型转化规律,完善了间接转直接带隙Ge实现方法的相关理论; 2)研究建立了准/直接带隙改性Ge的能带E-k模型,据此所获相关结论可为发光二极管、激光器件仿真模型提供关键参数; 3)提出了准/直接带隙改性Ge的带隙调制方案,为准/直接带隙改性Ge单片同层光电集成的实现提供了理论参考.本文的研究结果量化,可为准/直接带隙改性Ge材料物理的理解,以及Ge基光互连中发光器件有源层研究设计提供重要理论依据.     

Reverse current reduction of Ge photodiodes on Si without post-growth annealing Invited Paper

A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to ～10 mA/cm2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented "non-thermal" approach to reduce reverse current should accelerate electronics-photonics convergence by using Ge on the Si complementary metal oxide semiconductor (CMOS) platform.     

Junction field-effect-transistor-based germanium photodetector on silicon-on-insulator

We propose and demonstrate a novel Ge photodetector on silicon-on-insulator based on a junction field effect transistor structure, where the field-effect transistor gate is replaced by a Ge island with no contact on it. Light incident on the Ge switches on the device by altering the conductance of the Si channel through secondary photoconductivity. The device's sensitivity is also enhanced by a vast reduction in parasitic capacitance. In cw measurements, proof-of-concept detectors exhibit up to a 33% change in Si channel conductance by absorbing only 200 nW of power at 1.55 microm. In addition, pulsed response tests have shown that rise times as low as 40 ps can be achieved.     

First-order transition from a Kondo insulator to a ferromagnetic metal in single crystalline FeSi(1-x)Ge(x)

The phase diagram of FeSi(1-x)Ge(x), obtained from magnetic, thermal, and transport measurements on single crystals, shows a discontinuous transition from Kondo insulator to ferromagnetic metal with x at a critical concentration, x(c) approximately 0.25. The gap of the insulating phase strongly decreases with x. The specific heat gamma coefficient appears to track the density of states of a Kondo insulator. The phase diagram is consistent with an insulator-metal transition induced by a reduction of the hybridization with x in conjunction with disorder on the Si/Ge ligand site.     

Heteromaterial-gate line tunnel field-effect transistor based on Si/Ge heterojunction

A Si/Ge heterojunction line tunnel field-effect transistor(LTFET) with a symmetric heteromaterial gate is proposed.Compared to single-material-gate LTFETs, the heteromaterial gate LTFET shows an off-state leakage current that is three orders of magnitude lower, and steeper subthreshold characteristics, without degradation in the on-state current. We reveal that these improvements are due to the induced local potential barrier, which arises from the energy-band profile modulation effect. Based on this novel structure, the impacts of the physical parameters of the gap region between the pocket and the drain, including the work-function mismatch between the pocket gate and the gap gate, the type of dopant, and the doping concentration, on the device performance are investigated. Simulation and theoretical calculation results indicate that the gap gate material and n-type doping level in the gap region should be optimized simultaneously to make this region fully depleted for further suppression of the off-state leakage current.     

Poly-Si1-xGex栅应变SiN型金属-氧化物-半导体场效应管栅耗尽模型研究

基于对Poly-Si_1-xGe_x栅功函数的分析,通过求解Poisson方程, 获得了Poly-Si_1-xGe_x栅应变Si N型金属-氧化物-半导体场效应器件 (NMOSFET)垂直电势与电场分布模型.在此基础上,建立了考虑栅耗尽的Poly-Si_1-xGe_x栅应变Si NMOSFET的阈值电压模型和栅耗尽宽度及其归一化模型,并利用该模型,对器件几何结构参数、 物理参数尤其是Ge组分对Poly-Si_1-xGe_x栅耗尽层宽度的影响, 以及栅耗尽层宽度对器件阈值电压的影响进行了模拟分析.结果表明:多晶耗尽随Ge组分和栅掺杂浓度的增加而减弱, 随衬底掺杂浓度的增加而增强;此外,多晶耗尽程度的增强使得器件阈值电压增大. 所得结论能够为应变Si器件的设计提供理论依据.     

离子注入和固相外延制备Si1-x-yGexCy半导体薄膜

用等离子体增强化学气相淀积(PECVD)生长了200nm的SiGe薄膜,然后将C离子注入SiGe层,经两步热退火处理制备了Si1-x-yGexCy三元合金半导体薄膜.应用卢瑟福背散射(RBS),傅里叶变换红外光谱(FTIR)和高分辨率x射线衍射(HRXRD)研究了薄膜的结构和外延特性.发现C原子基本处于替代位置,C原子的掺入缓解了SiGe层的压应变 关键词： Si1-x-yGexCy薄膜 离子注入 固相外延     

Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si量子信道 异质结构 CMOSFET 量子论 量子阱strained SiGe/Si, quantum well channel, heterostructure CMOSFET, poly-SiGe gateProject supported by the Preresearch from National Ministries and Commissions (Grant Nos 51408061104DZ01, 51439010904DZ0101).2/2/2006 12:00:00 AM2006-01-022006-03-16A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Sil-xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including： 1） the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2） the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3） better transistor matching; and 4） flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Dangling bond modulating the electronic and magnetic properties of zigzag SiGe nanoribbon

First-principles nonmagnetic calculations reveal a metallic character in zigzag SiGe nanoribbons (ZSiGeNRs) regardless of their width. The partial DOS projected onto the Si and Ge atoms of ZSiGeNR shows that a sharp peak at the Fermi level is derived from the edge Si and Ge atoms. The charge density contours show the Si–Ge bond is covalent bond, while for the Si–H bond and Ge–H bond, the valence charges are strongly accumulated around H atoms due to their stronger 1 s potential and the higher electronegativity of 2.20 than that of 1.90 for Si atom and 2.01 for Ge atom, so that a significant charge transformation from Si or Ge atoms to H atoms and thus an ionic binding feature. Spin–polarization calculations show that the band structures of ZSiGeNR are modified by the dangling bonds. Compared with perfect ZSiGeNR which is a ferrimagnetic semiconductor, the bands of the ZSiGeNRs with bare Si edge, bare Ge edge, and bare Si and Ge edges shift up and nearly flat extra bands appear at the Fermi level. The ZSiGeNR with bare Si edge or bare Ge edge is a ferrimagnetic metal, while ZSiGeNR with bare Si and Ge edges is a nonmagnetic metal.     

高性能SOI基GePIN波导光电探测器的制备及特性研究

本文报道了在SOI衬底上外延高质量单晶Ge薄膜并制备高性能不同尺寸Ge PIN波导光电探测器.通过采用原子力显微镜、X射线衍射、拉曼散射光谱表征外延Ge薄膜的表面形貌、晶体质量以及应变参数,结果显示外延Ge薄膜中存在约0.2%左右的张应变,且表面平整,粗糙度为1.12 nm.此外,通过暗电流、光响应度以及3 dB带宽的测试来研究波导探测器的性能,结果表明尺寸为4μm×20μm波导探测器在-1 V的反向偏压下暗电流密度低至75 mA/cm~2,在1.55μm波长处的响应度为0.58 A/W,在-2 V的反向偏压下的3 dB带宽为5.5 GHz.     

Genetic-algorithm discovery of a direct-gap and optically allowed superstructure from indirect-gap Si and Ge semiconductors

Combining two indirect-gap materials-with different electronic and optical gaps-to create a direct gap material represents an ongoing theoretical challenge with potentially rewarding practical implications, such as optoelectronics integration on a single wafer. We provide an unexpected solution to this classic problem, by spatially melding two indirect-gap materials (Si and Ge) into one strongly dipole-allowed direct-gap material. We leverage a combination of genetic algorithms with a pseudopotential Hamiltonian to search through the astronomic number of variants of Si(n)/Ge(m)/…/Si(p)/Ge(q) superstructures grown on (001) Si(1-x)Ge(x). The search reveals a robust configurational motif-SiGe(2)Si(2)Ge(2)SiGe(n) on (001) Si(x)Ge(1-x) substrate (x≤0.4) presenting a direct and dipole-allowed gap resulting from an enhanced Γ-X coupling at the band edges.     

High-speed waveguide-integrated Ge/Si avalanche photodetector

Waveguide-integrated Ge/Si heterostructure avalanche photodetectors(APDs) were designed and fabricated using a CMOS-compatible process on 8-inch SOI substrate. The structure of the APD was designed as separate-absorption-chargemultiplication(SACM) using germanium and silicon as absorption region and multiplication region, respectively. The breakdown voltage(V_b) of such a device is 19 V at reverse bias and dark current appears to be 0.71 μA at 90% of the V_b. The device with a 10-μm length and 7-μm width of Ge layer shows a maximum 3-dB bandwidth of 17.8 GHz at the wavelength of 1550 nm. For the device with a 30-μm-length Ge region, gain-bandwidth product achieves 325 GHz.