Germanium MOSFETs With CeO2/HfO2/ TiN Gate Stacks

Long-channel Ge pMOSFETs and nMOSFETs were fabricated with high-kappa CeO₂/HfO₂/TiN gate stacks. CeO₂ was found to provide effective passivation of the Ge surface, with low diode surface leakage currents. The pMOSFETs showed a large I _ON/I_OFF ratio of 10⁶, a subthreshold slope of 107 mV/dec, and a peak mobility of approximately 90 cm² /Vmiddots at 0.25 MV/cm. The nMOSFET performance was compromised by poor junction formation and demonstrated a peak mobility of only ~3 cm²/Vmiddots but did show an encouraging I_ON/I _OFF ratio of 10⁵ and a subthreshold slope of 85 mV/dec     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

低温退火对具有HfO2/TiN栅结构的MOS电容电学性能的影响

The effects of low temperature annealing,such as post high-k dielectric deposition annealing(PDA),post metal annealing(PMA)and forming gas annealing(FGA)on the electrical characteristics of a metal–oxide–semiconductor(MOS)capacitor with a TiN metal gate and a HfO2dielectric are systematically investigated.It can be found that the low temperature annealing can improve the capacitance–voltage hysteresis performance significantly at the cost of increasing gate leakage current.Moreover,FGA could effectively decrease the interfacial state density and oxygen vacancy density,and PDA could make the flat band positively shift which is suitable for P-type MOSs.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Investigation of atomic vapour deposited TiN/HfO2/SiO2 gate stacks for MOSFET devices

HfO₂ films were grown by atomic vapour deposition (AVD) on SiO₂/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO₂ based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 10¹² cm⁻². The interface trap charge density of HfO₂/SiO₂ stacks can be reduced to 3 × 10¹¹ eV⁻¹ cm⁻² near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO₂/SiO₂ gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO₂ based PMOS transistors is 56 cm²/Vs.     

Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Observation and characterization of defects in HfO2 high-K gate dielectric layers

A deeper understanding of Hf-based high-K materials in terms of their structural and electrical defects is important for device implementation. We have studied the occurrence of such defects using wet-etch defect delineation, electron microscopy, depth-profiling and conventional electrical measurements. It is evident that defects are present in HfO₂ films that are related to the microstructure and stoichiometry of the film, which in turn depend on the deposition temperature, starting surface and post-deposition treatments. These results appear to be independent of the deposition technique. Two types of defects were observed, those that are physically visible and cause immediate failures especially on large-area structures, and those that cause high leakage but not immediate failures. The existence of defects affects not only leakage or performance but will also affect the reliability through trapping of charge at the defect sites. As films continue to be scaled thinner, the requirements on defect reduction to minimize electrical impact may become more stringent.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

High-quality MOSFETs with ultrathin LPCVD gate SiO2

MOSFETs and MOS capacitors with ultrathin (65 Å) low-pressure chemical vapor deposition (LPCVD) gate SiO₂ have been fabricated and compared to those with thermal SiO₂ of identical thickness. Results show that the devices with LPCVD SiO₂ have higher transconductance and current drivability, better channel hot-carrier immunity, lower defect density, and better time-dependent dielectric breakdown (TDDB) characteristics than devices with conventional thermal SiO₂     

Comparison of metal gate electrodes on MOCVD HfO2

Metal gate electrodes of sputtered aluminum (Al), titanium nitride (TiN) and nickel aluminum nitride (NiAlN) are investigated in this work. They are compared with respect to their compatibility with metal organic chemical vapor deposited (MOCVD) hafnium dioxide (HfO₂) gate dielectrics. TiN, with a midgap work function of 4.65 eV on SiO₂, exhibits promising characteristics as metal gate on HfO₂. In addition, encouraging results are presented for the ternary metal NiAlN, whereas classic Al electrodes are found unstable in conjunction with HfO₂.     

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

In this letter, an enhancement-mode(E-mode) GaN p-channel field-effect transistor(p-FET) with a high current density of-4.9 mA/mm based on a O₃-Al₂O₃/HfO₂(5/15 nm) stacked gate dielectric was demonstrated on a p⁺⁺-GaN/pGaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p⁺⁺-GaN capping layer, a good linear ohmic I-V characteristic featuring a low-contact resistivity(ρc) of 1.34 × 10^-4 Ω·cm² was obtain...     

Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Improved interface quality and charge-trapping characteristics of MOSFETs with high-/spl kappa/ gate dielectric

The effects of high-pressure annealing on interface properties and charge trapping of nMOSFET with high-/spl kappa/ dielectric were investigated. Comparing with conventional forming gas (H/sub 2//Ar=4%/96%) annealed sample, nMOSFET sample annealed in high-pressure (5-20 atm), pure H/sub 2/ ambient at 400/spl deg/C shows 10%-15% improvements in linear drain current (I/sub d/) and maximum transconductance (g/sub m,max/). Interface trap density and charge trapping properties were characterized with charge pumping measurements and "single pulsed" I/sub d/-V/sub g/ measurements where reduced interface state density and improved charge trapping characteristics were observed after high pressure annealing. These results indicate that high pressure pure hydrogen annealing can be a crucial process for future high-/spl kappa/ gate dielectric applications.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.     

Impact of the TiN electrode deposition on the HfO2 band gap for advanced MOSFET gate stacks

The impact of the deposition of a TiN electrode on the high-k oxide HfO₂ has been investigated, focussing on the dielectric band gap. After the gate elaboration, a non-destructive approach combining Spectroscopic Ellipsometry (SE), Reflection Electron Energy Loss Spectroscopy (REELS) and X-ray Photoelectron Spectroscopy (XPS) was developed to probe the buried metal/high-k interface. The overall optical band gap is 5.9 ± 0.1 eV with no change after the metal gate deposition. A local reduction of 1 eV is measured near the TiN layer, due to N diffusion at the interface creating N 2p states at the top of the HfO₂ valence band. Increased disorder and defects are identified in the high-k after gate elaboration by XPS, REELS and SE.