Full-chip leakage analysis for 65 nm CMOS technology and beyond

This work proposes a full-chip leakage analysis framework for 65 nm technology and beyond. Analytical models are first constructed to capture the impact of process parameters on leakage current. Then a methodology is introduced to characterize leakage-related process variations in a systematic manner. On such a basis, an efficient procedure is developed to analyze the state-dependent power dissipation due to leakage of a large circuit block by taking into account different leakage mechanisms. Unlike many traditional approaches that rely on log-normal approximations, the proposed algorithm applies a quadratic model of the logarithm for the full-chip leakage current. It is able to handle both Gaussian and non-Gaussian parameter distributions. The model is validated with test chips manufactured with a commercial 65 nm CMOS process. Validation results prove that the proposed modeling methodology could achieve a higher accuracy than that from existing methods. Moreover, a full-chip leakage analysis using the developed model can be orders of magnitude faster than a Monte Carlo based approach.     

亚65nm工艺新型p结构多米诺与门设计

利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态.     

应用于65nm CMOS技术节点漏电流分析的精确快速的查表模型

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into consideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technology. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in excellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.     

Accurate and fast table look-up models for leakage current analysis in 65 nm CMOS technology

Novel physical models for leakage current analysis in 65 nm technology are proposed. Taking into con-sideration the process variations and emerging effects in nano-scaled technology, the presented models are capable of accurately estimating the subthreshold leakage current and junction tunneling leakage current in 65 nm technol-ogy. Based on the physical models, new table look-up models are developed and first applied to leakage current analysis in pursuit of higher simulation speed. Simulation results show that the novel physical models are in ex-cellent agreement with the data measured from the foundry in the 65 nm process, and the proposed table look-up models can provide great computational efficiency by using suitable interpolation techniques. Compared with the traditional physical-based models, the table look-up models can achieve 2.5X speedup on average on a variety of industry circuits.     

功率器件漏电流的PEM定位和分析

光发射显微镜(PEM)系统是应用于微电子器件漏电流定位和分析的有效工具。利用PEM系统的激光光束诱导阻抗变化(OBIRCH)功能和光发射(EMMI)功能,从正面可直接对功率器件大的漏电流进行定位观察。利用PEM的EMMI功能,还可从背面对器件微弱的漏电流进行定位和分析。介绍了PEM系统对功率器件芯片不同量级的漏电流进行定位与分析的应用,为分析功率器件漏电流失效提供依据。     

亚65 nm及以下节点的光刻技术

由于193 nm浸入式光刻技术的迅速发展,它被业界广泛认为是65 nm和45 nm节点首选光刻技术.配合双重曝光技术,193 nm浸入式光刻技术还可能扩展到32 nm节点,但是光刻成本会成倍增长,成品率会下降.随着ASML在2006年推出全球第一款EUV曝光设备,人们纷纷看好EUV技术应用到32 nm及以下节点,但是它仍需克服很多技术和经济上的挑战.对于22 nm节点,电子束直写是最可行,成本最低的候选方案,业界将在它与EUV技术之间做出抉择.     

开关电源静态泄漏和动态功率建模与分析

随着器件尺寸的不断缩小,电路复杂度日益增加,电源已成为微处理器等需要精确供能的系统能否较快发展的主要制约因素之一.由于功耗是诸多不确定变量的函数,因此,芯片功率及宏功率分析最为准确的方法是基于制造过程和工作负荷变化的统计分析方法.与静态时序模型可以表示为一个线性规范化的高斯分布不同,统计分析是一个依赖于过程变量、工作量波动的复杂指数函数,这对统计能量分析是一个独特的挑战.提出了一种研究方法,通过研究开关电源的静态漏电功耗和动态功率统计分布,揭示宏功率分析与芯片功率分析的特征和相关性.实验结果表明,该方法对开关电源的研究是可行的.     

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method employs the orthogonal polynomials to represent the variational gate-level leakages in a closed form first, which is generated by a fast multi-dimensional Gaussian quadrature method. The total leakage currents then are computed by simply summing up the resulting orthogonal polynomials (their coefficients). Unlike many existing approaches, no grid-based partitioning and approximation are required. Instead, the spatial correlations are naturally handled by orthogonal decompositions. The proposed method is very efficient and it becomes linear in the presence of strong spatial correlations. Experimental results show that the proposed method is about 16× faster than the recently proposed method (Chang and Sapatnekar, 2005 [1]) with constant better accuracy.     

亚70nm CMOS工艺低漏电流、高噪声容限的低功耗多输入多米诺或门的设计

提出了两种新的电路技术,在降低多输入多米诺"或门"的动态功耗的同时减小了漏电流,并提高了电路的噪声容限.采用新的电路技术设计了八输入多米诺"或门"并基于45nm BSIM4 SPICE 模型对其进行了模拟.模拟结果表明,设计的两种新多米诺电路在同样的噪声容限下有效地降低了动态功耗,减小了总的漏电流,同时提高了工作速度.与双阈值多米诺电路相比,设计的两种电路动态功耗分别降低了8.8%和11.8%,电路速度分别提高了9.5%和13.7%,同时总的漏电流分别降低了80.8%和82.4%.基于模拟结果,也分析了双阈值多米诺电路中求值点的不同逻辑状态对总的漏电流的影响.     

45nm低功耗、高性能Zipper CMOS多米诺全加器设计

提出了电荷自补偿技术,此技术利用P型多米诺电路动态结点的放电对N型多米诺电路的动态结点充电,并在此技术基础上综合应用双阈值技术和多电源电压技术,设计了新型低功耗、高性能Zipper CMOS多米诺全加器.仿真过程中提出了功耗分布法,精确找到了电荷自补偿技术的最优路径.仿真结果表明,在相同的时间延迟下,与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比,新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7%,静态功耗分别减小了41%,20%和43%.最后,分析并得到了新型全加器漏电流最低的输入矢量和时钟状态.     

氧化铝陶瓷封接强度的统计分析

采用Weibull分布和正态分布,对氧化铝陶瓷封接强度进行统计分析,并通过Weibull模数和变异系数来表征了材料强度的离散性。同时通过Weibull分布,比较了标准组合抗拉强度、拉钉强度和抗折强度测试的数据。     

Fullerene Resist Materials for the 32 nm Node and Beyond

Current resist materials cannot simultaneously meet the sensitivity, resolution and line width roughness (LWR) requirements set out by the International Technology Roadmap for Semiconductors (ITRS) for the 32nm node and beyond. Here we present a fullerene‐based, chemically amplified resist system, which demonstrates the potential to fulfill these requirements for next generation lithography. A chemically amplified fullerene resist was prepared, consisting of the derivative MF07‐01, an epoxide crosslinker, and a photoacid generator, such as triarylsulfonium hexafluoroantimonate. The sensitivity of this resist was shown to be between 5 and 10 µC cm^?2 at 20 keV for various combinations of post‐application bake and post‐exposure bake conditions. Using 30 keV electron beam exposure, sparse patterns with 15 nm resolution were demonstrated, whilst for dense patterns a half‐pitch of 25 nm could be achieved. The LWR for the densely patterned features is ～4 nm. The etch durability of the fullerene CA system was shown to be comparable to that of SAL601, a common novolac‐based commercial resist, at almost four times that of silicon.     

提高谐波参量测量精度的谱泄漏相消算法

提出一种能有效提高谐波参量测量精度的新算法.该法通过两个采样起点约间隔半个信号周期的采样数据作加窗傅里叶变换,并利用它们将谱泄漏抵消,从而有效地改善谐波分析的精度.所提出的方法适用于任何形式的对称窗函数.理论分析与数值模拟结果均表明:该算法可显著提高容易被强谐波所掩蔽的弱谐波的谱分析精度从而提高谱分析的整体测量精度.     

择优生长的多晶硅压阻统计理论

本文报道了计算择优生长的多晶硅压阻灵敏度的统计平均理论,由此得到了〈100〉、〈110〉〈111〉、〈211〉、〈311〉、〈331〉等低指数晶向择优生长的p型和n型多晶硅的平均晶粒压阻系数.将这些结果应用到具有多重择优晶向的多晶硅材料,经过计算可进一步得到多晶硅力敏电阻的灵敏度.对于制作在矩形膜中心区域的一系列多晶硅电阻,实验得到的结果与理论分析的结果符合得很好.这些结果为多晶硅压阻型压力传感器的设计提供了有效的手段.     

超低漏电流超快恢复SiGeC功率二极管研究

 提出一种超低漏电流超快恢复SiGeC p-i-n二极管结构.基于异质结电流输运机制,该SiGeC二极管实现了低通态压降下高电流密度的传输,改善了二极管的反向恢复特性,同时具有较低的反向漏电流.与少子寿命控制技术相比,该器件有效协调了降低通态电压、减小反向漏电流、缩短反向恢复时间三者之间的矛盾.对不同温度下器件反向恢复特性研究结果表明,SiGeC二极管的反向恢复时间与同结构SiGe二极管相比,350K时缩短了1/3,400K时缩短了40%以上,器件的热稳定性显著提高,降低了对器件后续制作工艺的限制,有益于功率集成.     

65nm CMOS工艺单收单发IEEE802.11AC芯片的MAC控制器的设计实现

本文提出一种兼容IEEE80211AC SISO的无线局域网SOC芯片,芯片集成模拟前端、数字基带处理、媒体访问控制处理器模块,采用SMIC 65nm 1P6M CMOS工艺实现,测试结果表明,在正常工作条件下能提供较高的吞吐率、灵活的速率选择以及良好的兼容性,在标准IEEE802.11AC SISO模式下,测试所得UDP吞吐率为267M b/s。     

斯特林制冷机间隙密封泄漏量的影响因素权重分析

为分析斯特林制冷机间隙密封泄漏量影响因素权重,结合同心环形缝隙流动理论,确定影响因素包括间隙厚度、密封长度、间隙两端压差、转速、间隙内径以及活塞冲程.通过正交试验搭建32组数学模型,基于计算流体CFD数值模拟的方法,研究分析不同密封间隙的泄漏情况.利用方差分析对仿真结果进行处理,结果表明间隙厚度对斯特林制冷机的泄漏量影...     

基于符号分析和统计分析的宏模型自动建立方法

符号分析和统计分析是自动建立宏模型的常用方法．本文综合了这两种方法，提出一种新的宏模型自动建立方法，克服了分别利用以上两种方法建立宏模型的缺陷，使建立的宏模型具有更高的精度本文结出了应用新方法建立宏模型的实例，并与SPICE模拟结果进行了比较，以说明新方法的有效性．     

小目标与海空背景合成红外图像统计特性分析

针对海空复杂背景下红外小目标识别的需要,对海空背景及其小目标的红外图像特性进行了统计分析。具体分析了在有目标和无目标两种情况下3~5 μm和8~12 μm两个波段图像的均值、方差和协方差等统计特性以及图像的局部对比度、信杂比和阈值随探测距离变化的规律;同时对生成的红外热像进行了直方图分析。结果表明：随着探测距离的减小,导弹的辐射逐渐增大,到达一定探测距离时（大约8 200 m）可以从热像图中区分导弹的蒙皮辐射和羽流辐射。根据有目标和无目标两种情况下图像特性的差异,可以判断图像中是否存在目标,从而为目标识别提供了关于目标和背景的先验知识,研究结果可用于海空背景下红外小目标的检测。     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.