SiOx interlayer to enhance the performance of InGaZnO-TFT with AlOx gate insulator

We have fabricated indium–gallium–zinc (IGZO) thin film transistor (TFT) using SiO_x interlayer modified aluminum oxide (AlO_x) film as the gate insulator and investigated their electrical characteristics and bias voltage stress. Compared with IGZO-TFT with AlO_x insulator, IGZO-TFT with AlO_x/SiO_x insulator shows superior performance and better bias stability. The saturation mobility increases from 5.6 cm²/V s to 7.8 cm²/V s, the threshold voltage downshifts from 9.5 V to 3.3 V, and the contact resistance reduces from 132 Ωcm to 91 Ωcm. The performance improvement is attributed to the following reasons: (1) the introduction of SiO_x interlayer improves the insulator surface properties and leads to the high quality IGZO film and low trap density of IGZO/insulator interface. (2) The better interface between the channel and S/D electrodes is favorable to reduce the contact resistance of IGZO-TFT.     

Characterization of magnesium oxide gate insulators grown using RF sputtering for ZnO thin-film transistors

A ZnO thin-film transistor (TFT) with an MgO insulator was fabricated on a silicon (100) substrate using a radiofrequency magnetron sputtering system. The MgO insulator was deposited using the same deposition system; the total pressure during the deposition process was maintained at 5 mTorr, and the oxygen percentage of O₂/(Ar + O₂) was set at 30%, 50%, or 70%. The process temperature was maintained at below 300 °C. The dielectric constant of the MgO thin layer was approximately 11.35 with an oxygen percentage of 70%. This ZnO TFT displayed enhanced transistor properties, with a field-effect mobility of 0.0235 cm² V⁻¹ s⁻¹, an I_ON/I_OFF ratio of ∼10⁵, and an SS value of 1.18 V decade⁻¹; these properties were superior to those measured for the MgO insulators synthesized using oxygen percentages of 30% and 50%.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Enhancement of carrier mobility in pentacene thin-film transistor on SiO2 by controlling the initial film growth modes

Pentacene thin-film transistors (TFTs) were fabricated on thermally grown SiO₂ gate insulator under the conditions of various pre-cleaning treatments. Initial nucleation and growth of the material films on treated substrates were observed by atomic force microscope. The performance of fabricated TFT devices with different surface cleaning approaches was found to be highly related to the initial film morphologies. In contrast to the three-dimensional island-like growth mode on SiO₂ under an organic cleaning process, a layer-by-layer initial growth occurred on the SiO₂ insulator cleaned with ammonia solution, which was believed to be the origination of the excellent electrical properties of the TFT device. Field effect mobility of the TFT device could achieve as high as 1.0 cm²/Vs on the bared SiO₂/Si substrate and the on/off ratio was over 10⁶.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Ta2Si short time thermal oxidized layers in N2O and O2 to form high-k gate dielectric on SiC

In this work, we report on two properties of the oxidation of tantalum silicide (Ta₂Si) on SiC substrates making this material of interest as insulator for many wide bandgap or compound semiconductors. The relatively high oxidation rate of tantalum silicide to form high-k insulator layers and its ability for being oxidized in diluted N₂O ambient in a manner similar to the oxidation in O₂ are investigated. Metal-insulator-semiconductor capacitors have been used to establish the actual applicability and constrain of the high-k insulator depending on the oxidation conditions. At 1050 °C, the reduction of the oxidation time from 1 h to 5 min affects primordially the SiO_x interfacial layer formed between the bulk insulator and the substrate. This interfacial layer strongly influences the metal-insulator-semiconductor performances of the oxidized Ta₂Si layer. The bulk insulator basically remains unaffected although some structural differences arise when the oxidation is performed in N₂O.     

Improvement of electrical properties of silicon-based thin-film transistors by modifying technological fabrication processes

This paper is a review of technological process evolution associated to electrical performance improvement of silicon-based thin-film transistors (TFTs) that were performed mainly in the GM/IETR laboratory. The main objective in agreement with the fields of applications is to fabricate TFTs at a temperature low enough to be compatible with the substrates, glass substrates in a first place and flexible substrates in a second one, which implies several approaches. In fact, the electrical properties of the TFTs, mainly field-effect mobility of carriers in the channel, I _on/I _off drain current ratio, and subthreshold slope, are strongly dependent on the quality and the nature of the channel material, on the material quality and thus on the density of states at the interface with the gate insulator, and on the quality of the gate insulator itself. All the improvements are directly linked to all these aspects, which means an actual combination of the efforts. For the glass substrate, compatible technology processes such as deposition techniques, or solid phase, or laser crystallizations of active layers were studied and compared. The paper details all these approaches and electrical performances. In addition, some results about the use of a silicon–germanium compound as channel active layer and airgap transistors for which the insulator is released, complete the presentation of the evolution of the silicon-based TFTs during the last twenty years.     

Extraction of density-of-states in amorphous InGaZnO thin-film transistors from temperature stress studies

The instability of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with different active layer thicknesses under temperature stress has been investigated through using the density-of-states (DOS). Interestingly, the a-IGZO TFT with 22 nm active layer thickness showed a better stability than the others, which was observed from the decrease of interfacial and semiconductor bulk trap densities. The DOS was calculated based on the experimentally-obtained activation energy (E_A), which can explain the experimental observations. We developed the high-performance Al₂O₃ TFT with 22 nm IGZO channel layer (a high mobility of 7.4 cm²/V, a small threshold voltage of 2.8 V, a high I_on/I_off 1.8 × 10⁷, and a small SS of 0.16 V/dec), which can be used as driving devices in the next-generation flat panel displays.     

Effects of laser pulse wavelength and laser fluence on the characteristics of silver nanoparticle generated by laser ablation

Electrically pumped ultraviolet random lasing was achieved in metal-insulator-semiconductor (MIS) diodes based on ZnO films at room temperature. The ZnO films were grown by plasma assisted molecular beam epitaxy. Two different kinds of insulator layers, SiO _x (0<x≤2) and AlO _x (0<x≤1.5) were deposited by electron beam evaporation. X-ray diffraction experiments found these oxide layers were amorphous (or microcrystals), and X-ray photoelectron spectroscopy confirmed the Si and Al were fully oxidized. Compared with devices using SiO _x as the insulator layer, diodes with evaporated AlO _x layers showed a lower working threshold forward current (～20 mA to ～26 mA) and higher emission intensity. Periodic features indicating formation of closed-loop paths were deduced by the power Fourier transform of electroluminescence spectra. The cavity length of both devices increased as forward currents increased, while a larger cavity length was always obtained in the AlO _x -involved device under the same working current. The improved performance was attributed to larger hole amount in AlO _x layers. These results revealed that evaporated AlO _x can serve as good electron blocking and hole supplying layers for hetero-structures.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.     

Surface-modified lead–zirconium-titanate system for solution-processed ferroelectric-gate thin-film transistors

We propose the use of a La₂O₃ (LO) film as the capping layer for improvement of a semiconductor/insulator interface in a solution-processed indium–tin–oxide (ITO) ferroelectric-gate thin-film transistor (FGT) device. It is demonstrated that the LO layer acts as a good barrier film not only for preventing the interdiffusion between the ITO semiconductor and lead–zirconium-titanate (PZT) insulator layers, but also for stabilizing the PZT surface structure. The fabricated FGT device exhibited high I _on/I _off, large M _w, high μ _FE and improved retention time of about 10⁹, 3.5 V, 7.94 cm²?V^?1?s^?1 and 1 day, respectively, which are comparable to or better than those obtained with FGTs fabricated by means of conventional vacuum processes. We also point out that the key origin of the interface improvement is likely due to the incorporation of La into the PZT system, forming a La surface-modified PZT system which is more stable than the pure PZT in terms of Pb volatility and formation of oxygen vacancies.     

Investigation of the electrical properties and stability of HfInZnO thin-film transistors

In this study, amorphous HfInZnO (a-HIZO) thin films and related thin-film transistors (TFTs) were fabricated using the RF-sputtering method. The effects of the sputtering power (50–200 W) on the structural, surface, electrical, and optical properties of the a-HIZO films and the performance and NBIS stability of the a-HIZO TFTs were investigated. The films’ N_e increased and resistivity decreased as the sputtering power increased. The 100 W deposited a-HIZO film exhibited good optical and electrical properties compared with other sputtering powers. Optimization of the 100 W deposited a-HIZO TFT demonstrated good device performance, including a desirable μ_FE of 19.5 cm²/Vs, low SS of 0.32 V/decade, low V_th of 0.8 V, and high I_on/I_off of 10⁷, respectively. The 100 W deposited a-HIZO TFT with Al₂O₃ PVL also exhibited the best stability, with small V_th shifts of -2.2 V during NBIS testing. These high-performance a-HIZO thin films and TFTs with Al₂O₃ PVL have practical applications in thin-film electronics.     

A comparative study of SELBOX-JLT and SOI-JLT

Analysis of thermal and electrical characteristics of the proposed device, selective buried oxide junctionless transistor (SELBOX-JLT) along with its analog performance, is compared with silicon on insulator junctionless transistor (SOI-JLT). The proposed device shows better thermal efficiency. The maximum device temperature of SELBOX-JLT is 311 K, much less than that of SOI-JLT (445 K). The proposed device has almost no effect of self-heating on output characteristics. SELBOX-JLT exhibits better I _ON/I _OFF ratio, subthreshold slope, and drain-induced barrier lowering as compared to SOI-JLT for the same channel length. The analog performance parameters as transconductance (G _m ), transconductance/drain current ratio (G _m /I _D), drain conductance (G _D), output resistance (R ₀), intrinsic gain (G _m R ₀), and unity-gain frequency (f _T ) of the proposed device are found to be better than SOI-JLT.     

Improvement of electrical characteristics of InGaZnO thin film transistors by using HMDSO/O2 plasma deposited SiOCH buffer layer

In this work, we present the performance improved InGaZnO thin film transistors by inserting low temperature processed 10 nm thick SiOCH buffer layers between SiN_x insulator and InGaZnO channel layer. The influences of oxygen flow rate during the deposition of SiOCH buffer layer have been intensively investigated. Basing on the analysis of hall effect measurement and Fourier transform infrared spectrum, the SiOCH buffer layer can effectively increase the carrier concentration of the channel layer by the hydrogen doping due to re-sputtering and diffusion effect. The InGaZnO thin film transistor with buffer layer exhibits an enhanced performance with mobility of 13.09 cm²/vs, threshold voltage of −0.55 V and I_on/I_off over 10⁶.     

A thin-film transistor with a very thin a-Si:H layer and its application for an LC panel

One of the disadvantages of applying an a-Si:H thin-film transistor (TFT) to an active matrix-addressed liquid crystal (LC) panel is that a TFT with an a-Si:H has a very large photo-leakage current because of the high photo-conductivity of an a-Si:H itself.We have tried decreasing the photo-leakage current by varying the thickness of an a-Si:H layer (L) in TFTs and investigated the characteristics of TFTs, mainly drain voltage versus drain current containing photo-leakage current (I _ph).As a result, it is shown that lnI _ph is proportional to InL, and its gradient is 1.5–2.0. We assume that the thinner an a-Si:H layer is, the more effective the recombination of carriers at the interface states is forI _ph.We have applied TFT with a very thin a-Si:H layer (30nm) to a full-color active matrix-addressed LC panel for a moving picture display and realized a display of good quality under illuminated condition of 5×10⁴lx without a shading layer in it.     

Analysis of interface states and series resistance for Al/PVA:n-CdS nanocomposite metal–semiconductor and metal–insulator–semiconductor diode structures

This paper presents the fabrication and characterization of Al/PVA:n-CdS (MS) and Al/Al₂O₃/PVA:n-CdS (MIS) diode. The effects of interfacial insulator layer, interface states (N _ss ) and series resistance (R _s ) on the electrical characteristics of Al/PVA:n-CdS structures have been investigated using forward and reverse bias I–V, C–V, and G/w–V characteristics at room temperature. Al/PVA:n-CdS diode is fabricated with and without insulator Al₂O₃ layer to explain the effect of insulator layer on main electrical parameters. The values of the ideality factor (n), series resistance (R _s ) and barrier height (? _b ) are calculated from ln(I) vs. V plots, by the Cheung and Norde methods. The energy density distribution profile of the interface states is obtained from the forward bias I–V data by taking into account the bias dependence ideality factor (n(V)) and effective barrier height (? _e ) for MS and MIS diode. The N _ss values increase from mid-gap energy of CdS to the bottom of the conductance band edge for both MS and MIS diode.     

Forward and reverse bias current-voltage characteristics of Au/n-Si Schottky barrier diodes with and without SnO2 insulator layer

The effects of interfacial insulator layer, interface states (N_ss) and series resistance (R_s) on the electrical characteristics of Au/n-Si structures have been investigated using forward and reverse bias current-voltage (I-V) characteristics at room temperature. Therefore, Au/n-Si Schottky barrier diodes (SBDs) were fabricated as SBDs with and without insulator SnO₂ layer to explain the effect of insulator layer on main electrical parameters. The values of ideality factor (n), R_s and barrier height (Φ_Bo) were calculated from ln(I) vs. V plots and Cheung methods. The energy density distribution profile of the interface states was obtained from the forward bias I-V data by taking bias dependence of ideality factor, effective barrier height (Φ_e) and R_s into account for MS and MIS SBDs. It was found that N_ss values increase from at about mid-gap energy of Si to bottom of conductance band edge of both SBDs and the MIS SBD’s N_ss values are 5-10 times lower than those of MS SBD’s. An apparent exponential increase from the mid-gap towards the bottom of conductance band is observed for both SBDs’ (MS and MIS) interface states obtained without taking R_s into account.     

High performance IGZO/TiO2 thin film transistors using Y2O3 buffer layers on polycarbonate substrate

In this work, we fabricate IGZO TFT devices on flexible substrate at room temperature. The IGZO/TiO₂ TFT has small subthreshold swing of 0.16 V/dec, but suffers large gate leakage and negative threshold voltage. However, the TiO₂ TFT with Y₂O₃ buffer layers shows improved characteristics including a low threshold voltage of 0.55 V, a small sub-threshold swing of 0.175 V/decade and high field-effect mobility of 43 cm²/Vs. Such good performance can be attributed to the enhanced capacitance density and lowered gate leakage owing to the integration of large band gap Y₂O₃ and low-temperature higher-κ TiO₂.     

Comprehensive study of high-Tc interface superconductivity

Using ALL-MBE technique, we have synthesized different heterostructures consisting of an insulator La₂CuO₄ (I) and a metal La_1.56Sr_0.44CuO₄ (M) layer neither of which is superconducting by itself. The M-I bilayers were superconducting with a critical temperature T_c≈30-36 K. This highly robust phenomenon is confined within 1-2 nm from the interface and is primarily caused by the redistribution of doped holes across the interface. In this paper, we present a comprehensive study of the interface superconductivity by a range of experimental techniques including transport measurements of superconducting properties.     

Effect of Ge doping on the electrical properties of amorphous Zn–Sn–O thin films

We report the effect of germanium doping on the active layer of amorphous Zinc–Tin-Oxide (a-ZTO) thin film transistor (TFT). Amorphous thin film samples were prepared by RF magnetron sputtering using single targets composed of Zn₂Ge_0.05Sn_0.95O₄ and Zn₂SnO₄ with variable oxygen contents in the sputtering gases. In comparison with undoped, Ge-doped a-ZTO films exhibited five order of magnitude lower carrier density with a significantly higher Hall-mobility, which might be due to suppressed oxygen vacancies in the a-ZTO lattice since the Ge substituent for the Sn site has relatively higher oxygen affinity. Thus, the bulk and interface trap densities of Ge-doped a-ZTO film were decreased one order of magnitude to 7.047 × 10¹⁸ eV⁻¹cm⁻³ and 3.52 × 10¹¹ eV⁻¹cm⁻², respectively. A bottom-gate TFT with the Ge-doped a-ZTO active layer showed considerably improved performance with a reduced SS, positively shifted V_th, and two orders of magnitude increased I_on/I_off ratio, attributable to the doped Ge ions.