基于CMOS工艺的RF接收机架构设计

分析了RF接收机的直流抑制、闪烁噪声及镜像抑制问题。给出了采用低中频接收机结构来抑制直流闪烁噪声，同时配合数字中频处理技术来控制镜像抑制的设计方法。     

L波段数字声广播接收机CMOS集成模拟前端

本文设计了使用CMOS工艺,单片集成的L波段数字声广播(DAB)接收机模拟前端.接收机前端应用了三种方法来提高镜像抑制度:低中频双正交weaver结构比一般的同相/正交(I/Q)两路下变频结构具有更高的镜像抑制能力;镜像抑制低噪声放大器(LNA)提供了额外的镜像信号抑制;具有相位和幅度校正功能的本振驱动器提供了更精确的正交本振信号.仿真显示接收机前端对镜像信号的抑制超过65dB,其级联噪声指数为4dB,输出三阶交调指数为22dBm.接收机前端使用TSMC 0.25μm CMOS工艺制作,版图核心面积为9mm²,目前正在测试中.     

全集成CMOS SCA接收机单片化探讨

本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。     

一种0.18μm CMOS工艺单电感单模块正交卫星导航接收机射频前端设计

本文介绍了一种改进的单模块化卫星导航射频前端模块的设计.该结构将低噪声放大器,混频器以及压控振荡器层叠级联,并实现电流和功能的复用.仅采用了单个片上螺旋电感作为LC振荡回路,另外增加一个二分电路作为正交本振信号的产生源.文章讨论了该模块的增益规划,噪声系数,以及设计的细节.对相位噪声以及功耗进行了改进.通过0.18μm CMOS射频工艺进行流片验证,获得带内平均噪声系数为5.4dB,增益43dB,三阶交调点-39dBm.测得相位噪声在本振1MHz偏移处小于-105dBc/Hz.整体功耗小于19.8mW,工作电压为1.8V.实验结果证明满足卫星导航射频前端应用的需要.     

一种用于北斗导航接收机的全集成差分LNA

基于SMIC 180 nm CMOS工艺,设计了一款用于北斗导航接收机射频前端的低噪声放大器。在该低噪声放大器中,所有电感均为片上实现,提高了集成度;采用差分结构,提升了共模噪声抑制能力。LNA的输入和输出均为50 Ω标准阻抗匹配。测试结果表明,当频率为1.27 GHz时,该LNA的功率增益为15 dB,噪声系数(NF)为2.3 dB,1dB压缩点(P1dB)为－6 dBm。差分电路单路功耗为25 mW,芯片面积为1.2 mm²。     

用于低中频GPS接收机的CMOS闪烁型模数转换器

模数转换器引入的信噪比的降低会直接影响GPS接收机的灵敏度,需仔细设计以减小信噪比的降低。采用TSMC0.25μm CMOS单层多晶硅五层金属工艺设计了一个用于低中频GPS接收机的CMOS4bit16.368MHz闪烁型模数转换器。实现一个高性能闪烁型模数转换器的关键是得到一个低功耗、低回程噪声、低失调电压的前置放大器和比较器电路,因此重点放在了提出的新的前置放大器和比较器的设计和优化上。在时钟采样率16.368MHz和输入信号频率4.092MHz的条件下,转换器测试得到的信噪失真比为24.7dB,无杂散动态范围为32.1dB,积分非线性为 0.31/-0.46LSB,,差分非线性为 0.66/-0.46LSB,功耗为3.5mW。转换器占用芯片面积0.07mm2。测试结果表明了该模数转换器的有效性,并已成功应用于GPS接收机芯片中。     

基于0.25μm MS/RF CMOS工艺的光电单片集成接收机设计

设计了一种单片集成的光电接收机芯片.在同一衬底上制作了基于同一工艺的光电二极管与接收机电路,以消除混合集成引入的寄生影响.这种单片集成接收机采用了先进的深亚微米MS/RF(混合信号/射频)CMOS工艺,利用这种新型工艺提供的新技术对原有光电二极管进行了改进,使其部分性能显著改善,并对整个光电集成芯片性能的提高有所帮助.     

一种基于0.18μm CMOS工艺低功耗多频点兼容GNSS卫星导航系统接收机射频前端模块设计

本文介绍了一种全集成的L波段多频点全球卫星导航系统(Global navigation satellite system, GNSS)接收机的射频前端模块的设计和实现.该模块采用了低中频,单射频通道的设计,包括一级低噪声放大器,一级下变频器以及多相滤波器和求和电路.其中低噪声放大器采用改进的带有源极负反馈的共源共栅极结构,并保证多频点兼容且共用片外匹配网络,并通过开关进行不同工作频点的切换.另外重新设计了可用于宽带的双平衡混频器作为下变频器,其在增益,噪声和线性度等方面进行了改进.采用TSMC 0.18μm 1P4M RF CMOS进行流片,对兼容1.27GHz和1.575GHz双模低中频射频前端模块结构进行相关设计的验证.相关测试表明,对于两个工作频点,本模块可以分别提供约45dB或43dB增益,噪声系数为3.35dB或3.9dB.同时,该模块在1.8V电压下电流为11.8mA到13.5mA. 射频模块的面积仅为1.91×0.53 mm²而整体芯片面积为2.45×2.36 mm².完全满足卫星导航接收机的应用需求.     

用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现

首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为 0.31/-0.46LSB,差分非线性为 0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.     

基于0.25μm MS/RF CMOS工艺的光电单片集成接收机设计

设计了一种单片集成的光电接收机芯片.在同一衬底上制作了基于同一工艺的光电二极管与接收机电路,以消除混合集成引入的寄生影响.这种单片集成接收机采用了先进的深亚微米MS/RF(混合信号/射频)CMOS工艺,利用这种新型工艺提供的新技术对原有光电二极管进行了改进,使其部分性能显著改善,并对整个光电集成芯片性能的提高有所帮助.     

一款低噪声卫星导航接收机射频前端的设计

基于0.18tm RF CMOS工艺,采用低中频系统结构,设计了一款可应用于全球定位导航系统(GPS) L1频段和北斗二代(BD2) B1频段的低噪声卫星导航接收机的射频模拟前端芯片.该前端包括低噪声放大器、无源混频器、中频放大器、复数带通滤波器和数控可变增益放大器.其中低噪声放大器采用电流舵技术,与无源混频器一起,提高了射频前端的1 dB压缩点输入功率(Pi(1dB)),有效地改善了系统的线性度.测试结果显示,在GPS L1频点,系统的最大增益107.2 dB,噪声系数达到1.8 dB,动态增益66 dB,镜像抑制比约为39.54 dB,Pi(1dB)为-41 dBm,电源为1.8V时,消耗电流16 mA,芯片面积1.7 mm×0.8 mm.     

Dual-Antenna RF CMOS Front-End for Interferer Removal in Ultra-Wideband Systems

Many ultra-wideband (UWB) systems are challenged by strong jammers and narrowband interferers. Using two antennas, we demonstrate a robust UWB radio frequency (RF) front-end design in a 0.25 μm mixed-signal complementary metal oxide semiconductor (CMOS) technology. The proposed realization is capable of adaptively removing a high-power, narrowband interferer early in the receiver chain avoiding front-end saturation and preserving UWB signal power. The early interferer removal resulting in interferer-free demodulation is based on the least mean squares (LMS) algorithm and achieved through a novel combiner low-noise amplifier and noise optimized filtering. Circuit level RF simulations of the proposed circuitry indicate a maximum improvement in signal-to-interference ratio of 39.6 dB.     

Integrated Front-End Receiver for a Portable Ultrasonic System

This paper concerns the design, the implementation and the validation of a fully integrated front-end receiver for a portable ultrasonic system. This front-end receiver includes a logarithmic preamplification circuit and followed by a programmable-gain compensator. The proposed building blocks largely amplify small amplitude signals, and moderately the large amplitude ones. They also compensate signal attenuation due to its traveling of several human body tissues. The ultrasonic receiver is implemented in CMOS 0.35 m technology. Spectre simulations of the front-end receiver show unity gain bandwidth higher than 100 MHz when driving a load of 1 pF. The expected measurements of the fabricated chip are reported. This chip operates at 3.3 V supply voltages, while maintaining wide common mode rejection ratio, high gain and low input offset voltage. The total power consumption is 15.6 mW and the total chip area is 7.2 mm² including the digital part needed to program the TGC.     

基于90nm CMOS工艺的60GHz射频接收前端电路设计

设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59～64 GHz的微波信号下变频至5～10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5～17.5 dB,双边带噪声因子为6.4～7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

用于超外差接收机的低压、低功耗高动态范围CMOS线性可变增益放大器

针对超外差接收机的自动增益控制网络,设计了一种结构简单的低压、低功耗全差分可变增益放大器.它由6级子电路级联而成,提供范围为81dB的数字控制增益,每一档为3dB,增益误差小于0.5dB.该电路工作于中频300kHz下,工作电压为1.8V,功耗仅为1.35mW.采用TSMC 0.18μm 1P6M CMOS工艺制造,芯片面积约为0.24mm2,低功耗及小芯片面积使其极适用于便携式通信系统的应用.测试结果达到设计要求.     

一种新的卫星导航系统快速选星方法

 从几何精度因子(GDOP)与星座几何布局的关系出发,提出了用于多星座卫星导航系统的快速选星方法——几何布局选星法.该方法以满足定位要求为前提,按卫星在星座中均布为原则来进行选星.仿真结果表明,相对传统GDOP选星法,计算量减少99%以上,而GDOP满足要求,同时,选星数较少且简洁快速,有效满足了选星求解的实时性和精度要求.     

A CMOS adaptive RF front-end receiver for wireless applications

The performance of signal-processing algorithms implemented in hardware depends on the efficiency of datapath, memory speed and address computation. Pattern of data access in signal-processing applications is complex and it is desirable to execute the innermost loop of a kernel in a single-clock cycle. This necessitates the generation of typically three addresses per clock: two addresses for data sample/coefficient and one for the storage of processed data. Most of the Reconfigurable Processors, designed for multimedia, focus on mapping the multimedia applications written in a high-level language directly on to the reconfigurable fabric, implying the use of same datapath resources for kernel processing and address generation. This results in inconsistent and non-optimal use of finite datapath resources. Presence of a set of dedicated, efficient Address Generator Units (AGUs) helps in better utilisation of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This article focuses on the design and application-specific integrated circuit implementation of address generators for complex addressing modes required by multimedia signal-processing kernels. A novel algorithm and hardware for AGU is developed for accessing data and coefficients in a bit-reversed order for fast Fourier transform kernel spanning over log?₂ N stages, AGUs for zig-zag-ordered data access for entropy coding after Discrete Cosine Transform (DCT), convolution kernels with stored/streaming data, accessing data for motion estimation using the block-matching technique and other conventional addressing modes. When mapped to hardware, they scale linearly in gate complexity with increase in the size.