An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.     

Crosstalk bandwidth and stability analysis in graphene nanoribbon interconnects

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate

A highly accurate closed-form approximation of frequency-dependent mutual impedance per unit length of a lossy silicon substrate coplanar-strip IC interconnects is developed. The derivation is based on a quasi-stationary full-wave analysis and Fourier integral transformation. The derivation shows the mathematical approximations which are needed in obtaining the desired expressions. As a result, for the first time, we present a new simple, yet surprisingly accurate closed-form expression which yield accurate estimates of frequency-dependent mutual resistance and inductance per unit length of coupled interconnects for a wide range of geometrical and technological parameters. The developed formulas describe the mutual line impedance behaviour over the whole frequency range ( i.e. also in the transition region between the skin effect, slow wave, and dielectric quasi-TEM modes). The results have been compared with the reported data obtained by the modified quasi-static spectral domain approach and new CAD-oriented equivalent-circuit model procedure.     

Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier

This study develops a post-linearization technique to simultaneously improve the input third-order intercept point (IIP3) and image-rejection ratio (IRR) of a 17 GHz low noise amplifier (LNA) in a 0.18 μm standard CMOS process. A third-order intermodulation distortion (IMD3) compensator constructed by a second-order notch filter was proposed to achieve both high linearity and image reject (IR) of the cascode LNA. The correlation between the post-linearization and IR techniques is analyzed and discussed. The measured LNA achieved a gain of 16.5 dB, a noise figure (NF) of 4.58 dB, an IIP3 of 0 dBm, and an IRR from 68 to 78 dB. The improvements of IIP3 and IRR are 11.7 and 46 dB, respectively, better than that of the LNA without the notch filter. The proposed IR LNA with total current dissipation of 4.8 mA under 1.8 V supply voltage and notch filter only dissipate a DC power of 2 mW.