面向低功耗的全加器优化设计

在对现有全加器电路研究分析的基础上，提出了基于传输管逻辑的低功耗全加器。电路采用对称结构，平衡了电路延迟，消除了毛刺，降低了功耗。经PSPICE在0．24μm工艺下模拟仿真，与已发表的全加器电路的性能进行比较。测试结果表明，改进的新全加器功耗可减小77．5％，同时能耗也是最低的。     

Systematic synthesis of approximate adders and multipliers with accurate error calculations

In this study, we perform logic synthesis and area optimization of approximate ripple-carry adders and Wallace-tree multipliers with a given error constraint. We first implement approximate 1-bit adders having different error rates as building blocks of the proposed multi-bit adders and multipliers. In implementations, we exploit offsetting errors in carry and sum outputs of the adders. Also we take into account the probability of occurrence of input assignments. Using the implemented 1-bit adders, we systematically synthesize multi-bit adders and multipliers proceeding from the least to the most significant bits. We design the ripple-carry adders such that their successive 1-bit approximate adders cannot produce build-up errors. We design the Wallace-tree multipliers by considering the fact that their building blocks of 1-bit adders might have different probabilities of occurrence for different input assignments. As a result, the proposed adders and multipliers, implemented using the Cadence Genus tool with TSMC 0.18μ m CMOS technology, offer in average a 25% smaller circuit area, and correspondingly power consumption, compared to the circuits proposed in the literature by satisfying the same error constraint. We also evaluate the adders and multipliers in image processing applications as well as within artificial neural networks.     

Implementation of low power adder design and analysis based on power reduction technique

This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier.Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design.The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.     

Low depth, low power carry lookahead adders using threshold logic

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.     

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

Full adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these adder modules are not only providing Low-Power dissipation and high speed but also full-voltage swing.     

Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs

Software implementation costs of most algorithms, designed for image compression in wireless sensor networks, do not justify their use to reduce the energy consumption and delay transmission of images. Even though the hardware solution looks to be very attractive for this problem, a specific care should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to respect the energy constraints of image transmission over wireless sensor networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) circuits.     

High-speed full adder based on minority function and bridge style for nanoscale

In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells. In addition the proposed structure improves the robustness and reduces sensitivity to the process variations of the other Bridge-Cap Full Adder cell already presented in the literature.     

Low power and high speed multiplier design with row bypassing and parallel architecture

This paper presents a low power and high speed row bypassing multiplier. The primary power reductions are obtained by tuning off MOS components through multiplexers when the operands of multiplier are zero. Analysis of the conventional DSP applications shows that the average of zero input of operand in multiplier is 73.8 percent. Therefore, significant power consumption can be reduced by the proposed bypassing multiplier. The proposed multiplier adopts ripple-carry adder with fewer additional hardware components. In addition, the proposed bypassing architecture can enhance operating speed by the additional parallel architecture to shorten the delay time of the proposed multiplier. Both unsigned and signed operands of multiplier are developed. Post-layout simulations are performed with standard TSMC 0.18 μm CMOS technology and 1.8 V supply voltage by Cadence Spectre simulation tools. Simulation results show that the proposed design can reduce power consumption and operating speed compared to those of counterparts. For a 16×16 multiplier, the proposed design achieves 17 and 36 percent reduction in power consumption and delay, respectively, at the cost of 20 percent increase of chip area in comparison with those of conventional array multipliers. In addition, the proposed design achieves averages of 11 and 38 percent reduction in power consumption and delay with 46 percent less chip area in comparison with those counterparts for both unsigned and signed multipliers. The proposed design is suitable for low power and high speed arithmetic applications.     

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.     

Adaptive power gating of 32-bit Kogge Stone adder

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16 nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area.     

High performance 8 bit cascaded carry look ahead adder with precise power consumption

Multiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be replaced with fast adders as carry‐look‐ahead adder (CLA). Power consumption in digital circuits depends on the number of metal–oxide–semiconductor field‐effect transistor employed and various other parameters. If number of metal–oxide–semiconductor field‐effect transistor is reduced the power consumption would definitely be reduced. Conventional CLAs would consume significant amount of power that still needs to be improved. The paper here deals with the implementation of 8 bit CLA with the aim of reducing the size and to precise the power consumption within nanowatt range, by improving the fundamental components of the circuit. All the parameters have been calculated by using Cadence Virtuoso tool at 45 nm technology. Copyright © 2014 John Wiley & Sons, Ltd.     

一种基于LTCC技术的新型功率放大器研制

将低温共烧陶瓷(LTCC)技术引入功率放大器的设计中,充分利用LTCC优势,将有源器件、无源器件、电气布线、微波链路全部集成在LTCC的多层结构中,真正意义上实现了功放的小型化、一体化设计,极大地提高了功放的可靠性。测试结果表明,基于该技术的两路放大器合成效率可达80%。     

A novel low-power full-adder cell for low voltage

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.     

A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption

In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture, the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off levels.

一种新型混合型有源电力滤波器的研究

提出了一种单相并联混合型有源电力滤波器的电路结构.该电路由有源滤波器与基波串联谐振支路并联再与无源滤波电路串联构成,用于抑制非线性整流负载产生的谐波电流流入电源侧.在该电路中,无源滤波器分担大部分抑制谐波和无功补偿的任务,减少了有源滤波器的容量;有源电力滤波器用于改善无源滤波器的滤波效果,抑制它与系统阻抗可能发生的谐振.实验结果表明,该混合型有源滤波器充分发挥了无源滤波器和有源滤波器各自优点,改善了无源滤波器的滤波性能,同时使有源滤波器不再承受基波电压,最大限度地减少了有源滤波器的容量,从而使有源电力滤波器可应用于大功率场合.     

浮点加法器的低功耗结构设计

浮点加法器是集成电路数据通道中重要的单元，它的性能和功耗极大地影响着处理器和数字信号处理器的性能。文章分析了浮点加法器的几种结构，重点介绍了实现低功耗的三数据通道结构。最后，还对浮点加法器结构的实用性进行了分析。     

Grounded capacitance multipliers based on active elements

In this study, we present two new grounded capacitance multiplier circuits based on a negative-type second-generation current conveyor (CCII-) and an inverting second-generation current conveyor (ICCII). The first proposed circuit consists of one CCII- and a voltage follower (VF) employing two NMOS transistors while the second proposed circuit is composed of an ICCII and an inverting voltage follower (IVF) including two NMOS transistors. Each circuit contains two resistors, and single grounded capacitor, which is attractive for integrated circuit realization. No active and passive component matching conditions are required for the realization of the proposed capacitance multiplier circuits. The simulation results are included to confirm the theory.     

一个异步低功耗微控制器的结构设计与VLSI实现

介绍了一个低功耗微控制器的结构设计与VLSI电路实现。适当地选择并设计了微控制器的体系结构和流水线,同时采用了异步逻辑的电路实现方法。该微控制器与PIC16C61的指令集兼容,功能相仿。在Chartered0.6μm 的工艺条件下,平均功耗只有PIC16C61的16％。与其它各种类型的现有微控制器相比,功耗的下降更为明显。     

LOGICAL SYNTHESIS OF MOLTIVALUED SYMMETRIC FUNCTION BASED ON BINARY FULL ADDERS

This paper discusses the definition and properties of multivalued symmetric functions, points out that a multivalued symmetric function can be decomposed according to the value of the function j. The subfunction Lj corresponding to j must be a symmetric function, and it may be expressed as the sum of products form of degenerated multivalued fundamental symmetric functions. Based on this consideration, the circuit realization for the multivalued symmetric functions based on full adders is proposed.