On the assessment of various implants using 3D TCAD for FinFETs

This work deals with the junction and channel optimization on FinFET devices. The main objective was to show feasibility of a three-dimensional (3D) process simulation within the context of optimization of the device design and the underlying fabrication processes. The 3D simulation process flow is based on the development of the SOI based FinFET devices at Infineon. Similar to real devices, important 3D geometrical features, such as corner roundings and 3D facets have been introduced into the simulation setup, which is based on commercially available 3D process simulation software (Taurus 3D). The influence of various unit process steps, such as channel implant, and LDD implant on the electrical performance of the devices have been evaluated. Beside the successful demonstration of a functional 3D process simulation flow, detailed issues of process and device simulation methodology such as the usage of different dopant diffusion and mobility models are assessed. Finally, a comparison of the simulation results with electrical measurement data is performed which fairly shows excellent agreement.     

On the device design assessment of multigate FETs (MuGFETs) using full process and device simulation with 3D TCAD

A design evaluation is reported for multigate FETs (MuGFETs) by implementing a full process flow using a commercial three-dimensional technology CAD (TCAD) tool within the context of optimizing the device design and underlying fabrication processes. The simulation is based on and refers to the development of the SOI-based 30 nm MuGFET devices. Using our real process flow, various process simulation parameters from diffusion and activation models are first calibrated to the experimental data. Device simulations are then performed with varying fin doping, fin width, fin height, L_dd and halo implant tilt, and box thickness. For a given fin thickness and increasing fin height, the threshold voltage, off-current, delay and short channel effects (SCEs) remain approximately insensitive, while the on-current and transconductance increases approximately linearly with the increase in fin height. On the other hand drain-induced barrier lowering (DIBL), subthreshold slope (S) and off-current I_OFF are quite sensitive to the variations in fin width (at fixed fin height). We found that the lower L_dd and halo implant tilt angle (20–30°) are beneficial in reducing the SCEs and off-current. Finally, a comparison of the simulation results with electrical measurement data is presented, which shows fairly good agreement.     

一种新型的圆柱体全包围栅结型场效应管体管： 器件物理, 器件仿真, 器件工艺

We report the analysis and TCAD results of a gate-all-around cylindrical （GAAC） FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-10 nm sizes.     

A novel GAAC FinFET transistor: device analysis, 3D TCAD simulation, and fabrication

We report the analysis and TCAD results of a gate-all-around cylindrical (GAAC) FinFET with operation based on channel accumulation. The cylindrical channel of the GAAC FinFET is essentially controlled by an infinite number of gates surrounding the cylinder-shaped channel. The symmetrical nature of the field in the channel leads to improved electrical characteristics, e.g. reduced leakage current and negligible corner effects. The Ion/Ioff ratio of the device can be larger than 106, as the key parameter for device operation. The GAAC FinFET operating in accumulation mode appears to be a good potential candidate for scaling down to sub-l0 nm sizes.     

基于TCAD软件的单层多晶EEPROM器件模拟分析

利用TCAD软件对单层多晶EEPROM器件特性进行了模拟分析,介绍了单层多晶EEPROM存储单元结构与原理的基础,针对TCAD软件中模拟分析单层多晶EEPROM器件特性时存在的困难,提出了一种两个MOS管外加电阻的等效模型来替代单层多晶EEPROM存储单元结构进行等效模拟.通过编程模拟了单层多晶EEPROM器件性能,模拟分析得到的特性曲线与理论曲线能较好吻合,验证了等效模型方案的可行性.     

Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

The impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization.     

用三维蒙特卡罗模拟栅-源/漏不对准对体硅FinFET器件性能的影响

We investigate the influence of gate-source/drain(G-S/D) misalignment on the performance of bulk fin field effect transistors(FinFETs) through the three-dimensional(3D) full band Monte Carlo simulator.Several scattering mechanisms,such as acoustic and optical phonon scattering,ionized impurity scattering,impact ionization scattering and surface roughness scattering are considered in our simulator.The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work.Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length.The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.     

“过程控制及仪表”课程混合式教学改革与探索

过程控制及仪表是自动化专业本科生的专业核心课程。课程主要内容包括检测和控制仪表的选择与确定方法，以及过程控制系统的建模与设计方法。根据多年的教学实践经验提出了基于线上线下混合式教学的课程改革思路与具体做法，以满足线上线下混合式教学模式与“两性一度”的要求，能够帮助学生更积极主动地参与到课程的深度学习中，提高了学生工程应用的高阶能力，进而提高教学质量。     

Statistical analysis of asynchronous pipelines in presence of process variation using formal models

Globally Asynchronous Locally Synchronous Network on Chip (GALS NoC) is one of the possible interconnect platforms in multiprocessor systems on a chip. Designing proper links and buffers in these circuits can improve their performance. An asynchronous pipeline is a key element in buffer designs. The type of pipeline and its size can influence the performance metrics such as power consumption and delay. However, asynchronous pipelines face some challenges such as performance evaluation, verification, and process variation. We consider a new formal model to overcome these challenges simultaneously. In this paper, a new statistical model for asynchronous pipelines based on Generalized Stochastic Petri Net (GSPN) has been developed. This model can be applied to different pipeline stages, in order to compare them based on the statistical analysis of performance metrics (power consumption and delay), and to analyze their performance and timing verification in presence of variation. We have explored various kinds of asynchronous pipelines, and their corresponding results show this model has reasonable accuracy in average (below 5%) and in variance, compared to the low level Monte Carlo Hspice simulation.     

3D structuring of polymer parts using thermoforming processes

A new technique for the realization of complex three dimensional (3D) structures in polymer materials is presented. The described process can be applied for the fabrication of 3D structured foils as well as for 3D structured polymer parts using a replica molding process. In the first step, the foil is structured by Hot Embossing. This structured foil is then blown into a structured mold by pressure at high temperature, using a thermoforming process. The thermoforming process is realized in an especially designed tool, where different mold inserts can be applied. In the thermoforming process this tool, containing the mold insert and the structured foil is heated up and a pressure is applied which assures, that the foil covers the structured mold insert. Due to parameter optimization, high pattern fidelity can be achieved. As structures a porefield with a pore diameter of 500 nm and lines and spaces with a width of 1.6 μm were used. Besides a Moth Eye structure with a period of 280 nm and a blazed grating with a period of 1 μm and a blazed angle of 15° were imprinted and blown into the structured mold. The results show, that this process can be used to fabricate 3D structured foils with good structure fidelity. Besides the structured foils, additional poly(dimethylsiloxane) (PDMS) replications can be made out of this foils. These PDMS replications are used as stamps in a replica molding process. A micro fluidic system containing hydrophobic and hydrophilic channels was created using this process.     

三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响

本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。     

Bulk heterojunction formation with induced concentration gradient from a bilayer structure of P3HT:CdSe/ZnS quantum dots using inter-diffusion process for developing high efficiency solar cell

Bulk heterojunction (BHJ) solar cells consisting of poly(3-hexylthiophene) (P3HT) as donor and cadmium selenide/zinc sulphide (CdSe/ZnS) core shell quantum dots (QDs) as acceptor have been developed. Starting from the bilayer of P3HT/QD structure a BHJ is induced using the process of thermal inter-diffusion. The absorption measurements on the bilayer structure show that the absorption coefficient increases and the absorption spectrum becomes broader in the annealed device. Also, the photoluminescence of the annealed device is found to decrease by an order of magnitude showing a significant transfer of electrons to the QDs. With this approach and under broadband white light with an irradiance of 8.19 mW/cm², we have been able to achieve a power conversion efficiency of 5.1% and fill factor 0.45 for this solar cell.     

天线微小通道冷板金属3D打印成型工艺研究

微小通道液冷散热技术是近年来电子设备热设计研究的热点,已逐渐用于高热流密度电子设备的散热.然而真正实现工程应用仍存在诸多困难,主要原因是与之匹配的工艺技术尚不完善.研究了天线铝合金微小通道冷板的3D打印技术,介绍了工艺流程,加工了多个小尺寸芯片和大尺寸天线阵面的微小通道冷板.经分析,3 D打印基本能实现复杂拓扑结构微小通道冷板的成型,但仍存在通道堵塞、表面凹坑和翘曲等问题.     

三维动态红外视景仿真中噪声的模拟

红外探测器噪声模拟是三维动态红外视景仿真工程开发中的难点。本文提出了一种红外探测器噪声的动态生成技术。首先通过对红外探测器图像序列进行计算和分析,提取出了图像序列的高斯随机噪声和椒盐噪声。然后在基于OSG平台开发的仿真视景中,采用渲染到纹理(RTT)技术为视口添加噪声“屏幕”。利用着色器技术生成高斯随机噪声并逐像素渲染,从而实现随机噪声的动态效果。椒盐噪声根据RTT纹理中的盲元标记直接在着色器中进行灰度渲染。仿真结果表明,本文方法模拟噪声的效果逼真,系统开销很小。本文方法为动态红外三维视景开发中的噪声模拟提供了一种可行的工程思路。     

激光熔池三维非稳态对流传热过程的数值模拟

建立了带有移动热源的激光熔池流体流动及传热过程三维非稳态数学模型。采用自适应网格技术离散求解动量方程，计算出了不同时刻激光熔池温度分布和速度分布。结果表明，激光熔池对流传热非稳态过程是一个预热过程，随着时间的推移，熔池最高温度不断升高，熔深和熔池半径不断增大。非稳态过程按时间先后次序分为3个阶段，初始阶段（加热熔化阶段）、准稳态阶段和快速升温阶段。准稳态阶段熔池形貌、温度分布和速度分布增加幅度不大，且持续时间比另两个阶段长，说明三维准稳态模型是三维非稳态模型的较好近似。计算结果与巳有的实验结果相比大体吻合。     

激光熔池三维非稳态对流传热过程的数值模拟

建立了带有移动热源的激光熔池流体流动及传热过程三维非稳态数学模型.采用自适应网格技术离散求解动量方程,计算出了不同时刻激光熔池温度分布和速度分布.结果表明,激光熔池对流传热非稳态过程是一个预热过程,随着时间的推移,熔池最高温度不断升高,熔深和熔池半径不断增大.非稳态过程按时间先后次序分为3个阶段初始阶段(加热熔化阶段)、准稳态阶段和快速升温阶段.准稳态阶段熔池形貌、温度分布和速度分布增加幅度不大,且持续时间比另两个阶段长,说明三维准稳态模型是三维非稳态模型的较好近似.计算结果与已有的实验结果相比大体吻合.     

风云三号(D)气象卫星微波湿温度计系统建模和仿真

针对风云三号卫星微波湿温度计,该文建立了全功率式微波辐射计系统的仿真模型,重点对热辐射噪声源、混频器、低噪放、滤波器与检波器等关键性器件进行了参数化建模。从信号处理的角度对全功率式微波辐射计的工作过程进行了模拟,并对仿真系统的输出功率、灵敏度和线性度进行评估与分析。通过与实际仪器的测试结果对比,验证了所提仿真模型的正确性。