Thermal impedance extraction for bipolar transistors

This paper describes a method for extracting the thermal impedance of bipolar transistors. The measurement is a two-step process: first the fractional temperature coefficients are calibrated at dc and then a transient step response is measured to extract the thermal spreading impedance. Measurement configurations and an example measurement cycle are shown. The measurement results can be fitted to multiple-pole models for use in compact circuit modeling in SPICE     

Collector models for bipolar transistors

Using Ryder's formula for drift velocity vs. electric field, the d.c. field and carrier densities in the collector of a bipolar transistor are calculated analytically for all possible bias conditions. This is accomplished by modeling the majority carrier distribution. The results are compared with computer calculations and fairly close agreement is found. The analytic calculations are used to make a detailed division of the (J_c, V_cb) plane into injection, depletion and scattering-limited drift velocity (SLDV) areas. It turns out that the doping level N_d and the collector width W determine the nature of this division of the (J_c, V_cb) plane.     

GaAsSb for heterojunction bipolar transistors

The advantages of using GaAsSb in heterojunction bipolar transistors (HBT) are discussed with emphasis on two recent experimental results in the AlGaAs/GaAsSb material system. The performances of a prototype n-p-n AlGaAs/GaAsSb/GaAs double HBT (DHBT) that exhibits stable current gain with maximum collector current density of 5×10 ⁴ A/cm², and a p-n-p AlGaAs/GaAs HBT with a superlattice GaAsSb emitter ohmic contact which has a specific contact resistivity of 5±1×10^-7 Ω-cm² across the sample, are examined     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz     

Herb's bipolar transistors

The profound influence of Herbert Kroemer's ideas on the development of high-performance bipolar transistors is described. The historical context and subsequent development of innovations such as the drift base, achieved through concentration gradients and later with semiconductor bandgap grading, the use of wide bandgap emitters, concepts of collector-up transistors, and the introduction of new heterojunction materials, are reviewed     

Silicon-on-insulator bipolar transistors

Thin-film lateral n-p-n bipolar transistors (BJT) have been fabricated in moving melt zone recrystallized silicon on a 0.5-µm silicon dioxide substrate thermally grown on bulk silicon. Current-voltage characteristics of devices with different base widths (5 and 10 µm) have been analyzed. The use of a metal gate over oxide covering the base region has allowed the devices to be operated as n-channel MOSFET's as well thus surface effects on device characteristics have been investigated under varying gate-bias voltages. Maximum dc current gain values of 2.5 were achieved with a 5-µm base width and values around 0.5 with a 10-µm base width. Higher gain values were impeded by onset of high-level injection which occurred at low currents because of light base doping of these devices.     

Measurement method for accurate extraction of the base-to-emitterintrinsic and peripheral capacitances of bipolar transistors

A simple measurement method to determine the intrinsic and peripheral emitter junction capacitances is described. The method is based on measurements of BJT's with different emitter geometries and is demonstrated on transistors of an advanced BiCMOS technology. The method can be applied directly to standard deep-submicrometer devices. No special test devices are required. By determining peripheral capacitance for different processes, the method enables the examination of process schemes designed to suppress the effect of the peripheral emitter on the transistor action. The method also provides a useful approach to monitor the scaling behavior of the intrinsic and peripheral capacitances. Results indicate the peripheral capacitance starts dominating the total capacitance as the emitter is scaled into the submicrometer range. For devices with quarter micron emitter widths, the peripheral capacitance is found to be 3 to 4 times higher than the intrinsic capacitance, and puts a fundamental limitation on device design     

Extended charge-control model for bipolar transistors

In modeling bipolar transistors the charge-control concept provides a means to predict dynamic behavior from a detailed knowledge of the steady state. As such, it is a first-order approximation lacking accuracy. It is shown that a considerable improvement can be obtained when the concept is extended by allowing time delays in the relations between controlling charges and terminal voltages and currents. It suffices to introduce two delays whose magnitudes can be determined or estimated from the steady-state solution. The increased range of validity of the extended charge-control model is demonstrated in detail, by confronting it with a rigorous model and comparing small-signal parameters.     

Distributed theory for microwave bipolar transistors

A transistor large enough in one dimension to span a length significant compared to a quarter wavelength within the device can be treated as two-coupled transmission lines. The general solution of such lines is applied here for the small-signal linear case treated as a classical boundary value problem of TEM waves on coupled lines, which are uniform but have no other restrictions regarding transmission line parameters, coupling, symmetry, similarity, or terminations. This solution is extended to include the parasitic inductance and capacitance usually present in connecting the device into a circuit. Electrical characteristics of a distributed device begin to deviate noticeably from those of the equivalent lumped device even at a relatively short electrical length. Computer simulation of a large distributed transistor indicates that, if properly employed, distributed effects in small-signal operation may lead to advantageous characteristics such as in device impedance levels, stability, and gain-band product. Other characteristics may prove to be disadvantageous or troublesome in large signal or class C operation. If unrecognized or ignored, distributed effects can result in highly unsatisfactory transistor operation. As microwave transistors increase in size and frequency capability, distributed effects will undoubtedly need to be taken increasingly into account.     

Parameter extraction on MOSFET transistors using a new optimised fit strategy

Classical parameter-extraction programs rely on the minimisation of the relative current deviation. However, since, especially for analogue applications, the slope of the IDS/VDS curve in the saturation region is at least equally important, a new fit strategy has been developed. This new fit strategy extracts a parameter set which optimises the current residual as well as the slope residual at every point.     

Saturation in bipolar transistors

A computer solution is obtained for the voltage drop across a saturated transistor as a function of IC/IB, on the assumption that the emitter and collector currents may each be expressed as a superposition of three voltage-dependent terms. The result, showing good agreement with experiment, is a family of curves with the base current as the variable parameter.     

Fully ion-implanted bipolar transistors

Technology for the fabrication of fully ion-implanted bipolar transistors with arsenic emitters and boron bases is described. This technology results in extremely uniform distributions of electrical parameters, e.g,, hFE= 113 with a standard deviation of 1.3 across a wafer. In addition, it can produce a wide range of doping profiles and hence, a wide range of device performance. Using very similar processing schedules, transistors with hFEfrom 20 to >5000 and with fT's from 1.5 to 8.1 GHz have been made. The features of implanted arsenic which make it an excellent emitter are: 1) it can be implanted to high doses with only a small deep side tail which has a negligible effect on the typical transistor base; 2) because of the concentration dependence of its diffusion constant, it forms a very abrupt profile after diffusion; and 3) when diffused a short distance (∼1000 Å) away from the implanted region, high-lifetime material can be incorporated into the emitter and hence, high-gain low-leakage transistors can be made. When the arsenic emitter is combined with a double-peaked boron-implanted base, precise independent control of the active and inactive base properties of the device can be achieved. This independence allows considerable latitude in the choice of device parameters for fully implanted bipolar transistors.     

Figure of merit for integrated bipolar transistors

The maximum frequency of operation, ω_max, which is the frequency of operation when the unilateral power gain goes to zero, and ω_T, the unity current gain-bandwidth product, are used as figures of merit for bipolar transistors. Both of these figures of merit are inadequate for state-of-the-art integrated bipolar devices. This is because ω_max is based on neutralizing the feedback between the transistor output and input circuitry by complex networks which are quite impractical in integrated circuits, and ω_T is obtained with the output short circuited and thus has no relevance to a practical application.In this paper, we argue the case for using ω_PT the frequency at which the power transferred between identical amplifiers goes to unity as a practical figure of merit for the integrated bipolar transistor.     

Scaling `ballistic' heterojunction bipolar transistors

Reducing length scales in npn heterojunction bipolar transistors leads to unexpected changes in the fundamental limits of device performance. Very high p-type carrier concentrations in the base result in a reduced inelastic electron scattering rate. In addition, there exists a maximum base/collector bias above which ballistic collector transport is not possible, and correct scaling requires the n-type collector contact to be unusually heavily doped     

High-low polysilicon-emitter SiGe-base bipolar transistors

Self-aligned heterojunction bipolar transistors with a high-low emitter profile consisting of a heavily doped polysilicon contact on top of a thin epitaxial emitter cap have been fabricated. The low doping in the single-crystal emitter cap allows a very high dopant concentration in the base with low emitter-base reverse leakage and low emitter-base capacitance. The thin emitter cap is contacted by heavily doped polysilicon to reduce the emitter resistance, the base current, and the emitter charge storage. A trapezoidal germanium profile in the base ensures a small base transit time and adequate current gain despite high base doping. The performance potential of this structure was simulated and demonstrated experimentally in transistors with near-ideal characteristics, very small reverse emitter-base leakage current, and 52-GHz peak f_max, and in unloaded ECL and NTL ring oscillators with 24- and 19-ps gate delays, respectively     

Submicron transferred-substrate heterojunction bipolar transistors

We report submicron transferred-substrate AlInAs/GaInAs heterojunction bipolar transistors (HBT's). Devices with 0.4-μm emitter and 0.4-μm collector widths have 17.5 dB unilateral gain at 110 GHz. Extrapolating at -20 dB/decade, the power gain cutoff frequency f_max is 820 GHz. The high f_max, results from the scaling of HBT's junction widths, from elimination of collector series resistance through the use of a Schottky collector contact, and from partial screening of the collector-base capacitance by the collector space charge     

Intermodulation in heterojunction bipolar transistors

The modeling of small-signal intermodulation distortion (IMD) in heterojunction bipolar transistors (HBTs) is examined. The authors show that IMD current generated in the exponential junction is partially canceled by IMD current generated in the junction capacitance, and that this phenomenon is largely responsible for the unusually good IMD performance of these devices. Thus, a nonlinear model of the HBT must characterize both nonlinearities accurately. Finally, the authors propose a nonlinear HBT model suitable for IDM calculations, show how to measure its parameters, and verify its accuracy experimentally     

Ion implanted GaAs bipolar transistors

GaAs n-p-n bipolar transistors were fabricated by ion implanting Be and Se into bulk n-type substrate material. Devices with mesa collectors exhibit a d.c. current gain hFE ? 8 and a reverse bias leakage current of less than 10 nA.